arch/arm/include/asm/arch-tegra/warmboot.h

   1 /*
   2  * (C) Copyright 2010, 2011
   3  * NVIDIA Corporation <www.nvidia.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _WARM_BOOT_H_
   9 #define _WARM_BOOT_H_
  10
  11 #define STRAP_OPT_A_RAM_CODE_SHIFT      4
  12 #define STRAP_OPT_A_RAM_CODE_MASK       (0xf << STRAP_OPT_A_RAM_CODE_SHIFT)
  13
  14 /* Defines the supported operating modes */
  15 enum fuse_operating_mode {
  16         MODE_PRODUCTION = 3,
  17         MODE_UNDEFINED,
  18 };
  19
  20 /* Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) */
  21 enum {
  22         HASH_LENGTH = 4
  23 };
  24
  25 /* Defines the storage for a hash value (128 bits) */
  26 struct hash {
  27         u32 hash[HASH_LENGTH];
  28 };
  29
  30 /*
  31  * Defines the code header information for the boot rom.
  32  *
  33  * The code immediately follows the code header.
  34  *
  35  * Note that the code header needs to be 16 bytes aligned to preserve
  36  * the alignment of relevant data for hash and decryption computations without
  37  * requiring extra copies to temporary memory areas.
  38  */
  39 struct wb_header {
  40         u32 length_insecure;    /* length of the code header */
  41         u32 reserved[3];
  42         struct hash hash;       /* hash of header+code, starts next field*/
  43         struct hash random_aes_block;   /* a data block to aid security. */
  44         u32 length_secure;      /* length of the code header */
  45         u32 destination;        /* destination address to put the wb code */
  46         u32 entry_point;        /* execution address of the wb code */
  47         u32 code_length;        /* length of the code */
  48 };
  49
  50 /*
  51  * The warm boot code needs direct access to these registers since it runs in
  52  * SRAM and cannot call other U-Boot code.
  53  */
  54 union osc_ctrl_reg {
  55         struct {
  56                 u32 xoe:1;
  57                 u32 xobp:1;
  58                 u32 reserved0:2;
  59                 u32 xofs:6;
  60                 u32 reserved1:2;
  61                 u32 xods:5;
  62                 u32 reserved2:3;
  63                 u32 oscfi_spare:8;
  64                 u32 pll_ref_div:2;
  65                 u32 osc_freq:2;
  66         };
  67         u32 word;
  68 };
  69
  70 union pllx_base_reg {
  71         struct {
  72                 u32 divm:5;
  73                 u32 reserved0:3;
  74                 u32 divn:10;
  75                 u32 reserved1:2;
  76                 u32 divp:3;
  77                 u32 reserved2:4;
  78                 u32 lock:1;
  79                 u32 reserved3:1;
  80                 u32 ref_dis:1;
  81                 u32 enable:1;
  82                 u32 bypass:1;
  83         };
  84         u32 word;
  85 };
  86
  87 union pllx_misc_reg {
  88         struct {
  89                 u32 vcocon:4;
  90                 u32 lfcon:4;
  91                 u32 cpcon:4;
  92                 u32 lock_sel:6;
  93                 u32 reserved0:1;
  94                 u32 lock_enable:1;
  95                 u32 reserved1:1;
  96                 u32 dccon:1;
  97                 u32 pts:2;
  98                 u32 reserved2:6;
  99                 u32 out1_div_byp:1;
 100                 u32 out1_inv_clk:1;
 101         };
 102         u32 word;
 103 };
 104
 105 /*
 106  * TODO: This register is not documented in the TRM yet. We could move this
 107  * into the EMC and give it a proper interface, but not while it is
 108  * undocumented.
 109  */
 110 union scratch3_reg {
 111         struct {
 112                 u32 pllx_base_divm:5;
 113                 u32 pllx_base_divn:10;
 114                 u32 pllx_base_divp:3;
 115                 u32 pllx_misc_lfcon:4;
 116                 u32 pllx_misc_cpcon:4;
 117         };
 118         u32 word;
 119 };
 120
 121
 122 /**
 123  * Save warmboot memory settings for a later resume
 124  *
 125  * @return 0 if ok, -1 on error
 126  */
 127 int warmboot_save_sdram_params(void);
 128
 129 int warmboot_prepare_code(u32 seg_address, u32 seg_length);
 130 int sign_data_block(u8 *source, u32 length, u8 *signature);
 131 void wb_start(void);    /* Start of WB assembly code */
 132 void wb_end(void);      /* End of WB assembly code */
 133
 134 #endif