arch/arm/include/asm/armv8/mmu.h

   1 /*
   2  * (C) Copyright 2013
   3  * David Feng <fenghua@phytium.com.cn>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _ASM_ARMV8_MMU_H_
   9 #define _ASM_ARMV8_MMU_H_
  10
  11 /*
  12  * block/section address mask and size definitions.
  13  */
  14
  15 /* PAGE_SHIFT determines the page size */
  16 #undef  PAGE_SIZE
  17 #define PAGE_SHIFT              12
  18 #define PAGE_SIZE               (1 << PAGE_SHIFT)
  19 #define PAGE_MASK               (~(PAGE_SIZE - 1))
  20
  21 /***************************************************************/
  22
  23 /*
  24  * Memory types
  25  */
  26 #define MT_DEVICE_NGNRNE        0
  27 #define MT_DEVICE_NGNRE         1
  28 #define MT_DEVICE_GRE           2
  29 #define MT_NORMAL_NC            3
  30 #define MT_NORMAL               4
  31
  32 #define MEMORY_ATTRIBUTES       ((0x00 << (MT_DEVICE_NGNRNE * 8)) |     \
  33                                 (0x04 << (MT_DEVICE_NGNRE * 8))   |     \
  34                                 (0x0c << (MT_DEVICE_GRE * 8))     |     \
  35                                 (0x44 << (MT_NORMAL_NC * 8))      |     \
  36                                 (UL(0xff) << (MT_NORMAL * 8)))
  37
  38 /*
  39  * Hardware page table definitions.
  40  *
  41  */
  42
  43 #define PTE_TYPE_MASK           (3 << 0)
  44 #define PTE_TYPE_FAULT          (0 << 0)
  45 #define PTE_TYPE_TABLE          (3 << 0)
  46 #define PTE_TYPE_PAGE           (3 << 0)
  47 #define PTE_TYPE_BLOCK          (1 << 0)
  48 #define PTE_TYPE_VALID          (1 << 0)
  49
  50 #define PTE_TABLE_PXN           (1UL << 59)
  51 #define PTE_TABLE_XN            (1UL << 60)
  52 #define PTE_TABLE_AP            (1UL << 61)
  53 #define PTE_TABLE_NS            (1UL << 63)
  54
  55 /*
  56  * Block
  57  */
  58 #define PTE_BLOCK_MEMTYPE(x)    ((x) << 2)
  59 #define PTE_BLOCK_NS            (1 << 5)
  60 #define PTE_BLOCK_NON_SHARE     (0 << 8)
  61 #define PTE_BLOCK_OUTER_SHARE   (2 << 8)
  62 #define PTE_BLOCK_INNER_SHARE   (3 << 8)
  63 #define PTE_BLOCK_AF            (1 << 10)
  64 #define PTE_BLOCK_NG            (1 << 11)
  65 #define PTE_BLOCK_PXN           (UL(1) << 53)
  66 #define PTE_BLOCK_UXN           (UL(1) << 54)
  67
  68 /*
  69  * AttrIndx[2:0]
  70  */
  71 #define PMD_ATTRINDX(t)         ((t) << 2)
  72 #define PMD_ATTRINDX_MASK       (7 << 2)
  73 #define PMD_ATTRMASK            (PTE_BLOCK_PXN          | \
  74                                  PTE_BLOCK_UXN          | \
  75                                  PMD_ATTRINDX_MASK      | \
  76                                  PTE_TYPE_VALID)
  77
  78 /*
  79  * TCR flags.
  80  */
  81 #define TCR_T0SZ(x)             ((64 - (x)) << 0)
  82 #define TCR_IRGN_NC             (0 << 8)
  83 #define TCR_IRGN_WBWA           (1 << 8)
  84 #define TCR_IRGN_WT             (2 << 8)
  85 #define TCR_IRGN_WBNWA          (3 << 8)
  86 #define TCR_IRGN_MASK           (3 << 8)
  87 #define TCR_ORGN_NC             (0 << 10)
  88 #define TCR_ORGN_WBWA           (1 << 10)
  89 #define TCR_ORGN_WT             (2 << 10)
  90 #define TCR_ORGN_WBNWA          (3 << 10)
  91 #define TCR_ORGN_MASK           (3 << 10)
  92 #define TCR_SHARED_NON          (0 << 12)
  93 #define TCR_SHARED_OUTER        (2 << 12)
  94 #define TCR_SHARED_INNER        (3 << 12)
  95 #define TCR_TG0_4K              (0 << 14)
  96 #define TCR_TG0_64K             (1 << 14)
  97 #define TCR_TG0_16K             (2 << 14)
  98 #define TCR_EPD1_DISABLE        (1 << 23)
  99
 100 #define TCR_EL1_RSVD            (1 << 31)
 101 #define TCR_EL2_RSVD            (1 << 31 | 1 << 23)
 102 #define TCR_EL3_RSVD            (1 << 31 | 1 << 23)
 103
 104 #ifndef __ASSEMBLY__
 105 static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
 106 {
 107         asm volatile("dsb sy");
 108         if (el == 1) {
 109                 asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
 110                 asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
 111                 asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
 112         } else if (el == 2) {
 113                 asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
 114                 asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
 115                 asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
 116         } else if (el == 3) {
 117                 asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
 118                 asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
 119                 asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
 120         } else {
 121                 hang();
 122         }
 123         asm volatile("isb");
 124 }
 125
 126 struct mm_region {
 127         u64 virt;
 128         u64 phys;
 129         u64 size;
 130         u64 attrs;
 131 };
 132
 133 extern struct mm_region *mem_map;
 134 void setup_pgtables(void);
 135 u64 get_tcr(int el, u64 *pips, u64 *pva_bits);
 136 #endif
 137
 138 #endif /* _ASM_ARMV8_MMU_H_ */