arch/arm/include/asm/imx-common/iomux-v3.h

   1 /*
   2  * Based on Linux i.MX iomux-v3.h file:
   3  * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
   4  *                      <armlinux@phytec.de>
   5  *
   6  * Copyright (C) 2011 Freescale Semiconductor, Inc.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __MACH_IOMUX_V3_H__
  12 #define __MACH_IOMUX_V3_H__
  13
  14 #include <common.h>
  15
  16 /*
  17  *      build IOMUX_PAD structure
  18  *
  19  * This iomux scheme is based around pads, which are the physical balls
  20  * on the processor.
  21  *
  22  * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
  23  *   things like driving strength and pullup/pulldown.
  24  * - Each pad can have but not necessarily does have an output routing register
  25  *   (IOMUXC_SW_MUX_CTL_PAD_x).
  26  * - Each pad can have but not necessarily does have an input routing register
  27  *   (IOMUXC_x_SELECT_INPUT)
  28  *
  29  * The three register sets do not have a fixed offset to each other,
  30  * hence we order this table by pad control registers (which all pads
  31  * have) and put the optional i/o routing registers into additional
  32  * fields.
  33  *
  34  * The naming convention for the pad modes is SOC_PAD_<padname>__<padmode>
  35  * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
  36  *
  37  * IOMUX/PAD Bit field definitions
  38  *
  39  * MUX_CTRL_OFS:            0..11 (12)
  40  * PAD_CTRL_OFS:           12..23 (12)
  41  * SEL_INPUT_OFS:          24..35 (12)
  42  * MUX_MODE + SION + LPSR: 36..41  (6)
  43  * PAD_CTRL + NO_PAD_CTRL: 42..59 (18)
  44  * SEL_INP:                60..63  (4)
  45 */
  46
  47 typedef u64 iomux_v3_cfg_t;
  48
  49 #define MUX_CTRL_OFS_SHIFT      0
  50 #define MUX_CTRL_OFS_MASK       ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
  51 #define MUX_PAD_CTRL_OFS_SHIFT  12
  52 #define MUX_PAD_CTRL_OFS_MASK   ((iomux_v3_cfg_t)0xfff << \
  53         MUX_PAD_CTRL_OFS_SHIFT)
  54 #define MUX_SEL_INPUT_OFS_SHIFT 24
  55 #define MUX_SEL_INPUT_OFS_MASK  ((iomux_v3_cfg_t)0xfff << \
  56         MUX_SEL_INPUT_OFS_SHIFT)
  57
  58 #define MUX_MODE_SHIFT          36
  59 #define MUX_MODE_MASK           ((iomux_v3_cfg_t)0x3f << MUX_MODE_SHIFT)
  60 #define MUX_PAD_CTRL_SHIFT      42
  61 #define MUX_PAD_CTRL_MASK       ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
  62 #define MUX_SEL_INPUT_SHIFT     60
  63 #define MUX_SEL_INPUT_MASK      ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
  64
  65 #define MUX_MODE_SION           ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \
  66         MUX_MODE_SHIFT)
  67 #define MUX_PAD_CTRL(x)         ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
  68
  69 #define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs,  \
  70                 sel_input, pad_ctrl)                                    \
  71         (((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT)     |   \
  72         ((iomux_v3_cfg_t)(mux_mode)      << MUX_MODE_SHIFT)         |   \
  73         ((iomux_v3_cfg_t)(pad_ctrl_ofs)  << MUX_PAD_CTRL_OFS_SHIFT) |   \
  74         ((iomux_v3_cfg_t)(pad_ctrl)      << MUX_PAD_CTRL_SHIFT)     |   \
  75         ((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)|   \
  76         ((iomux_v3_cfg_t)(sel_input)     << MUX_SEL_INPUT_SHIFT))
  77
  78 #define NEW_PAD_CTRL(cfg, pad)  (((cfg) & ~MUX_PAD_CTRL_MASK) | \
  79                                         MUX_PAD_CTRL(pad))
  80
  81 #define __NA_                   0x000
  82 #define NO_MUX_I                0
  83 #define NO_PAD_I                0
  84
  85 #define NO_PAD_CTRL             (1 << 17)
  86
  87 #define IOMUX_CONFIG_LPSR       0x20
  88 #define MUX_MODE_LPSR           ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
  89                                 MUX_MODE_SHIFT)
  90 #ifdef CONFIG_MX7
  91
  92 #define IOMUX_LPSR_SEL_INPUT_OFS 0x70000
  93
  94 #define PAD_CTL_DSE_1P8V_140OHM   (0x0<<0)
  95 #define PAD_CTL_DSE_1P8V_35OHM    (0x1<<0)
  96 #define PAD_CTL_DSE_1P8V_70OHM    (0x2<<0)
  97 #define PAD_CTL_DSE_1P8V_23OHM    (0x3<<0)
  98
  99 #define PAD_CTL_DSE_3P3V_196OHM   (0x0<<0)
 100 #define PAD_CTL_DSE_3P3V_49OHM    (0x1<<0)
 101 #define PAD_CTL_DSE_3P3V_98OHM    (0x2<<0)
 102 #define PAD_CTL_DSE_3P3V_32OHM    (0x3<<0)
 103
 104 #define PAD_CTL_SRE_FAST     (0 << 2)
 105 #define PAD_CTL_SRE_SLOW     (0x1 << 2)
 106
 107 #define PAD_CTL_HYS       (0x1 << 3)
 108 #define PAD_CTL_PUE       (0x1 << 4)
 109
 110 #define PAD_CTL_PUS_PD100KOHM  ((0x0 << 5) | PAD_CTL_PUE)
 111 #define PAD_CTL_PUS_PU5KOHM    ((0x1 << 5) | PAD_CTL_PUE)
 112 #define PAD_CTL_PUS_PU47KOHM   ((0x2 << 5) | PAD_CTL_PUE)
 113 #define PAD_CTL_PUS_PU100KOHM  ((0x3 << 5) | PAD_CTL_PUE)
 114
 115 #else
 116
 117 #ifdef CONFIG_MX6
 118
 119 #define PAD_CTL_HYS             (1 << 16)
 120
 121 #define PAD_CTL_PUS_100K_DOWN   (0 << 14 | PAD_CTL_PUE)
 122 #define PAD_CTL_PUS_47K_UP      (1 << 14 | PAD_CTL_PUE)
 123 #define PAD_CTL_PUS_100K_UP     (2 << 14 | PAD_CTL_PUE)
 124 #define PAD_CTL_PUS_22K_UP      (3 << 14 | PAD_CTL_PUE)
 125 #define PAD_CTL_PUE             (1 << 13 | PAD_CTL_PKE)
 126 #define PAD_CTL_PKE             (1 << 12)
 127
 128 #define PAD_CTL_ODE             (1 << 11)
 129
 130 #if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)
 131 #define PAD_CTL_SPEED_LOW       (0 << 6)
 132 #else
 133 #define PAD_CTL_SPEED_LOW       (1 << 6)
 134 #endif
 135 #define PAD_CTL_SPEED_MED       (2 << 6)
 136 #define PAD_CTL_SPEED_HIGH      (3 << 6)
 137
 138 #define PAD_CTL_DSE_DISABLE     (0 << 3)
 139 #define PAD_CTL_DSE_240ohm      (1 << 3)
 140 #define PAD_CTL_DSE_120ohm      (2 << 3)
 141 #define PAD_CTL_DSE_80ohm       (3 << 3)
 142 #define PAD_CTL_DSE_60ohm       (4 << 3)
 143 #define PAD_CTL_DSE_48ohm       (5 << 3)
 144 #define PAD_CTL_DSE_40ohm       (6 << 3)
 145 #define PAD_CTL_DSE_34ohm       (7 << 3)
 146
 147 /* i.MX6SL/SLL */
 148 #define PAD_CTL_LVE             (1 << 1)
 149 #define PAD_CTL_LVE_BIT         (1 << 22)
 150
 151 /* i.MX6SLL */
 152 #define PAD_CTL_IPD_BIT         (1 << 27)
 153
 154 #elif defined(CONFIG_VF610)
 155
 156 #define PAD_MUX_MODE_SHIFT      20
 157
 158 #define PAD_CTL_INPUT_DIFFERENTIAL (1 << 16)
 159
 160 #define PAD_CTL_SPEED_MED       (1 << 12)
 161 #define PAD_CTL_SPEED_HIGH      (3 << 12)
 162
 163 #define PAD_CTL_SRE             (1 << 11)
 164
 165 #define PAD_CTL_ODE             (1 << 10)
 166
 167 #define PAD_CTL_DSE_150ohm      (1 << 6)
 168 #define PAD_CTL_DSE_75ohm       (2 << 6)
 169 #define PAD_CTL_DSE_50ohm       (3 << 6)
 170 #define PAD_CTL_DSE_37ohm       (4 << 6)
 171 #define PAD_CTL_DSE_30ohm       (5 << 6)
 172 #define PAD_CTL_DSE_25ohm       (6 << 6)
 173 #define PAD_CTL_DSE_20ohm       (7 << 6)
 174
 175 #define PAD_CTL_PUS_47K_UP      (1 << 4 | PAD_CTL_PUE)
 176 #define PAD_CTL_PUS_100K_UP     (2 << 4 | PAD_CTL_PUE)
 177 #define PAD_CTL_PUS_22K_UP      (3 << 4 | PAD_CTL_PUE)
 178 #define PAD_CTL_PKE             (1 << 3)
 179 #define PAD_CTL_PUE             (1 << 2 | PAD_CTL_PKE)
 180
 181 #define PAD_CTL_OBE_IBE_ENABLE  (3 << 0)
 182 #define PAD_CTL_OBE_ENABLE      (1 << 1)
 183 #define PAD_CTL_IBE_ENABLE      (1 << 0)
 184
 185 #else
 186
 187 #define PAD_CTL_DVS             (1 << 13)
 188 #define PAD_CTL_INPUT_DDR       (1 << 9)
 189 #define PAD_CTL_HYS             (1 << 8)
 190
 191 #define PAD_CTL_PKE             (1 << 7)
 192 #define PAD_CTL_PUE             (1 << 6 | PAD_CTL_PKE)
 193 #define PAD_CTL_PUS_100K_DOWN   (0 << 4 | PAD_CTL_PUE)
 194 #define PAD_CTL_PUS_47K_UP      (1 << 4 | PAD_CTL_PUE)
 195 #define PAD_CTL_PUS_100K_UP     (2 << 4 | PAD_CTL_PUE)
 196 #define PAD_CTL_PUS_22K_UP      (3 << 4 | PAD_CTL_PUE)
 197
 198 #define PAD_CTL_ODE             (1 << 3)
 199
 200 #define PAD_CTL_DSE_LOW         (0 << 1)
 201 #define PAD_CTL_DSE_MED         (1 << 1)
 202 #define PAD_CTL_DSE_HIGH        (2 << 1)
 203 #define PAD_CTL_DSE_MAX         (3 << 1)
 204
 205 #endif
 206
 207 #define PAD_CTL_SRE_SLOW        (0 << 0)
 208 #define PAD_CTL_SRE_FAST        (1 << 0)
 209
 210 #endif
 211
 212 #define IOMUX_CONFIG_SION       0x10
 213
 214 #define GPIO_PIN_MASK           0x1f
 215 #define GPIO_PORT_SHIFT         5
 216 #define GPIO_PORT_MASK          (0x7 << GPIO_PORT_SHIFT)
 217 #define GPIO_PORTA              (0 << GPIO_PORT_SHIFT)
 218 #define GPIO_PORTB              (1 << GPIO_PORT_SHIFT)
 219 #define GPIO_PORTC              (2 << GPIO_PORT_SHIFT)
 220 #define GPIO_PORTD              (3 << GPIO_PORT_SHIFT)
 221 #define GPIO_PORTE              (4 << GPIO_PORT_SHIFT)
 222 #define GPIO_PORTF              (5 << GPIO_PORT_SHIFT)
 223
 224 void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
 225 void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
 226                                      unsigned count);
 227 /*
 228 * Set bits for general purpose registers
 229 */
 230 void imx_iomux_set_gpr_register(int group, int start_bit,
 231                                          int num_bits, int value);
 232 #ifdef CONFIG_IOMUX_SHARE_CONF_REG
 233 void imx_iomux_gpio_set_direction(unsigned int gpio,
 234                                 unsigned int direction);
 235 void imx_iomux_gpio_get_function(unsigned int gpio,
 236                                 u32 *gpio_state);
 237 #endif
 238
 239 /* macros for declaring and using pinmux array */
 240 #if defined(CONFIG_MX6QDL)
 241 #define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
 242 #define SETUP_IOMUX_PAD(def)                                    \
 243 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {                           \
 244         imx_iomux_v3_setup_pad(MX6Q_##def);                     \
 245 } else {                                                        \
 246         imx_iomux_v3_setup_pad(MX6DL_##def);                    \
 247 }
 248 #define SETUP_IOMUX_PADS(x)                                     \
 249         imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2)
 250 #elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
 251 #define IOMUX_PADS(x) MX6Q_##x
 252 #define SETUP_IOMUX_PAD(def)                                    \
 253         imx_iomux_v3_setup_pad(MX6Q_##def);
 254 #define SETUP_IOMUX_PADS(x)                                     \
 255         imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
 256 #elif defined(CONFIG_MX6UL)
 257 #define IOMUX_PADS(x) MX6_##x
 258 #define SETUP_IOMUX_PAD(def)                                    \
 259         imx_iomux_v3_setup_pad(MX6_##def);
 260 #define SETUP_IOMUX_PADS(x)                                     \
 261         imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
 262 #else
 263 #define IOMUX_PADS(x) MX6DL_##x
 264 #define SETUP_IOMUX_PAD(def)                                    \
 265         imx_iomux_v3_setup_pad(MX6DL_##def);
 266 #define SETUP_IOMUX_PADS(x)                                     \
 267         imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
 268 #endif
 269
 270 #endif  /* __MACH_IOMUX_V3_H__*/