arch/arm/include/asm/imx-common/rdc-sema.h

   1 /*
   2  * Copyright (C) 2016 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:  GPL-2.0+
   5  */
   6
   7 #ifndef __RDC_SEMA_H__
   8 #define __RDC_SEMA_H__
   9
  10 /*
  11  * rdc_peri_cfg_t and rdc_ma_cft_t use the same layout.
  12  *
  13  *   [ 23 22 | 21 20 | 19 18 | 17 16 ] | [ 15 - 8 ] | [ 7 - 0 ]
  14  *      d3      d2      d1       d0    | master id  |  peri id
  15  *   d[x] means domain[x], x can be [3 - 0].
  16  */
  17 typedef u32 rdc_peri_cfg_t;
  18 typedef u32 rdc_ma_cfg_t;
  19
  20 #define RDC_PERI_SHIFT          0
  21 #define RDC_PERI_MASK           0xFF
  22
  23 #define RDC_DOMAIN_SHIFT_BASE   16
  24 #define RDC_DOMAIN_MASK         0xFF0000
  25 #define RDC_DOMAIN_SHIFT(x)     (RDC_DOMAIN_SHIFT_BASE + ((x << 1)))
  26 #define RDC_DOMAIN(x)           ((rdc_peri_cfg_t)(0x3 << RDC_DOMAIN_SHIFT(x)))
  27
  28 #define RDC_MASTER_SHIFT        8
  29 #define RDC_MASTER_MASK         0xFF00
  30 #define RDC_MASTER_CFG(master_id, domain_id) (rdc_ma_cfg_t)((master_id << 8) | \
  31                                         (domain_id << RDC_DOMAIN_SHIFT_BASE))
  32
  33 /* The Following macro definitions are common to i.MX6SX and i.MX7D */
  34 #define SEMA_GATES_NUM          64
  35
  36 #define RDC_MDA_DID_SHIFT       0
  37 #define RDC_MDA_DID_MASK        (0x3 << RDC_MDA_DID_SHIFT)
  38 #define RDC_MDA_LCK_SHIFT       31
  39 #define RDC_MDA_LCK_MASK        (0x1 << RDC_MDA_LCK_SHIFT)
  40
  41 #define RDC_PDAP_DW_SHIFT(domain)       ((domain) << 1)
  42 #define RDC_PDAP_DR_SHIFT(domain)       (1 + RDC_PDAP_DW_SHIFT(domain))
  43 #define RDC_PDAP_DW_MASK(domain)        (1 << RDC_PDAP_DW_SHIFT(domain))
  44 #define RDC_PDAP_DR_MASK(domain)        (1 << RDC_PDAP_DR_SHIFT(domain))
  45 #define RDC_PDAP_DRW_MASK(domain)       (RDC_PDAP_DW_MASK(domain) | \
  46                                          RDC_PDAP_DR_MASK(domain))
  47
  48 #define RDC_PDAP_SREQ_SHIFT     30
  49 #define RDC_PDAP_SREQ_MASK      (0x1 << RDC_PDAP_SREQ_SHIFT)
  50 #define RDC_PDAP_LCK_SHIFT      31
  51 #define RDC_PDAP_LCK_MASK       (0x1 << RDC_PDAP_LCK_SHIFT)
  52
  53 #define RDC_MRSA_SADR_SHIFT     7
  54 #define RDC_MRSA_SADR_MASK      (0x1ffffff << RDC_MRSA_SADR_SHIFT)
  55
  56 #define RDC_MREA_EADR_SHIFT     7
  57 #define RDC_MREA_EADR_MASK      (0x1ffffff << RDC_MREA_EADR_SHIFT)
  58
  59 #define RDC_MRC_DW_SHIFT(domain)        (domain)
  60 #define RDC_MRC_DR_SHIFT(domain)        (1 + RDC_MRC_DW_SHIFT(domain))
  61 #define RDC_MRC_DW_MASK(domain)         (1 << RDC_MRC_DW_SHIFT(domain))
  62 #define RDC_MRC_DR_MASK(domain)         (1 << RDC_MRC_DR_SHIFT(domain))
  63 #define RDC_MRC_DRW_MASK(domain)        (RDC_MRC_DW_MASK(domain) | \
  64                                          RDC_MRC_DR_MASK(domain))
  65 #define RDC_MRC_ENA_SHIFT       30
  66 #define RDC_MRC_ENA_MASK        (0x1 << RDC_MRC_ENA_SHIFT)
  67 #define RDC_MRC_LCK_SHIFT       31
  68 #define RDC_MRC_LCK_MASK        (0x1 << RDC_MRC_LCK_SHIFT)
  69
  70 #define RDC_MRVS_VDID_SHIFT     0
  71 #define RDC_MRVS_VDID_MASK      (0x3 << RDC_MRVS_VDID_SHIFT)
  72 #define RDC_MRVS_AD_SHIFT       4
  73 #define RDC_MRVS_AD_MASK        (0x1 << RDC_MRVS_AD_SHIFT)
  74 #define RDC_MRVS_VADDR_SHIFT    5
  75 #define RDC_MRVS_VADDR_MASK     (0x7ffffff << RDC_MRVS_VADDR_SHIFT)
  76
  77 #define RDC_SEMA_GATE_GTFSM_SHIFT       0
  78 #define RDC_SEMA_GATE_GTFSM_MASK        (0xf << RDC_SEMA_GATE_GTFSM_SHIFT)
  79 #define RDC_SEMA_GATE_LDOM_SHIFT        5
  80 #define RDC_SEMA_GATE_LDOM_MASK         (0x3 << RDC_SEMA_GATE_LDOM_SHIFT)
  81
  82 #define RDC_SEMA_RSTGT_RSTGDP_SHIFT     0
  83 #define RDC_SEMA_RSTGT_RSTGDP_MASK      (0xff << RDC_SEMA_RSTGT_RSTGDP_SHIFT)
  84 #define RDC_SEMA_RSTGT_RSTGSM_SHIFT     2
  85 #define RDC_SEMA_RSTGT_RSTGSM_MASK      (0x3 << RDC_SEMA_RSTGT_RSTGSM_SHIFT)
  86 #define RDC_SEMA_RSTGT_RSTGMS_SHIFT     4
  87 #define RDC_SEMA_RSTGT_RSTGMS_MASK      (0xf << RDC_SEMA_RSTGT_RSTGMS_SHIFT)
  88 #define RDC_SEMA_RSTGT_RSTGTN_SHIFT     8
  89 #define RDC_SEMA_RSTGT_RSTGTN_MASK      (0xff << RDC_SEMA_RSTGT_RSTGTN_SHIFT)
  90
  91 int imx_rdc_check_permission(int per_id, int dom_id);
  92 int imx_rdc_sema_lock(int per_id);
  93 int imx_rdc_sema_unlock(int per_id);
  94 int imx_rdc_setup_peri(rdc_peri_cfg_t p);
  95 int imx_rdc_setup_peripherals(rdc_peri_cfg_t const *peripherals_list,
  96                               unsigned count);
  97 int imx_rdc_setup_ma(rdc_ma_cfg_t p);
  98 int imx_rdc_setup_masters(rdc_ma_cfg_t const *masters_list, unsigned count);
  99
 100 #endif  /* __RDC_SEMA_H__*/