arch/arm/include/asm/mach-imx/iomux-v3.h

   1 /*
   2  * Based on Linux i.MX iomux-v3.h file:
   3  * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
   4  *                      <armlinux@phytec.de>
   5  *
   6  * Copyright (C) 2011 Freescale Semiconductor, Inc.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __MACH_IOMUX_V3_H__
  12 #define __MACH_IOMUX_V3_H__
  13
  14 #include <common.h>
  15
  16 /*
  17  *      build IOMUX_PAD structure
  18  *
  19  * This iomux scheme is based around pads, which are the physical balls
  20  * on the processor.
  21  *
  22  * - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
  23  *   things like driving strength and pullup/pulldown.
  24  * - Each pad can have but not necessarily does have an output routing register
  25  *   (IOMUXC_SW_MUX_CTL_PAD_x).
  26  * - Each pad can have but not necessarily does have an input routing register
  27  *   (IOMUXC_x_SELECT_INPUT)
  28  *
  29  * The three register sets do not have a fixed offset to each other,
  30  * hence we order this table by pad control registers (which all pads
  31  * have) and put the optional i/o routing registers into additional
  32  * fields.
  33  *
  34  * The naming convention for the pad modes is SOC_PAD_<padname>__<padmode>
  35  * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
  36  *
  37  * IOMUX/PAD Bit field definitions
  38  *
  39  * MUX_CTRL_OFS:            0..11 (12)
  40  * PAD_CTRL_OFS:           12..23 (12)
  41  * SEL_INPUT_OFS:          24..35 (12)
  42  * MUX_MODE + SION + LPSR: 36..41  (6)
  43  * PAD_CTRL + NO_PAD_CTRL: 42..59 (18)
  44  * SEL_INP:                60..63  (4)
  45 */
  46
  47 typedef u64 iomux_v3_cfg_t;
  48
  49 #define MUX_CTRL_OFS_SHIFT      0
  50 #define MUX_CTRL_OFS_MASK       ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
  51 #define MUX_PAD_CTRL_OFS_SHIFT  12
  52 #define MUX_PAD_CTRL_OFS_MASK   ((iomux_v3_cfg_t)0xfff << \
  53         MUX_PAD_CTRL_OFS_SHIFT)
  54 #define MUX_SEL_INPUT_OFS_SHIFT 24
  55 #define MUX_SEL_INPUT_OFS_MASK  ((iomux_v3_cfg_t)0xfff << \
  56         MUX_SEL_INPUT_OFS_SHIFT)
  57
  58 #define MUX_MODE_SHIFT          36
  59 #define MUX_MODE_MASK           ((iomux_v3_cfg_t)0x3f << MUX_MODE_SHIFT)
  60 #define MUX_PAD_CTRL_SHIFT      42
  61 #define MUX_PAD_CTRL_MASK       ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
  62 #define MUX_SEL_INPUT_SHIFT     60
  63 #define MUX_SEL_INPUT_MASK      ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
  64
  65 #define MUX_MODE_SION           ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \
  66         MUX_MODE_SHIFT)
  67 #define MUX_PAD_CTRL(x)         ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
  68
  69 #define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs,  \
  70                 sel_input, pad_ctrl)                                    \
  71         (((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT)     |   \
  72         ((iomux_v3_cfg_t)(mux_mode)      << MUX_MODE_SHIFT)         |   \
  73         ((iomux_v3_cfg_t)(pad_ctrl_ofs)  << MUX_PAD_CTRL_OFS_SHIFT) |   \
  74         ((iomux_v3_cfg_t)(pad_ctrl)      << MUX_PAD_CTRL_SHIFT)     |   \
  75         ((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)|   \
  76         ((iomux_v3_cfg_t)(sel_input)     << MUX_SEL_INPUT_SHIFT))
  77
  78 #define NEW_PAD_CTRL(cfg, pad)  (((cfg) & ~MUX_PAD_CTRL_MASK) | \
  79                                         MUX_PAD_CTRL(pad))
  80
  81 #define __NA_                   0x000
  82 #define NO_MUX_I                0
  83 #define NO_PAD_I                0
  84
  85 #define NO_PAD_CTRL             (1 << 17)
  86
  87 #define IOMUX_CONFIG_LPSR       0x20
  88 #define MUX_MODE_LPSR           ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
  89                                 MUX_MODE_SHIFT)
  90 #ifdef CONFIG_MX8M
  91 #define PAD_CTL_DSE0            (0x0 << 0)
  92 #define PAD_CTL_DSE1            (0x1 << 0)
  93 #define PAD_CTL_DSE2            (0x2 << 0)
  94 #define PAD_CTL_DSE3            (0x3 << 0)
  95 #define PAD_CTL_DSE4            (0x4 << 0)
  96 #define PAD_CTL_DSE5            (0x5 << 0)
  97 #define PAD_CTL_DSE6            (0x6 << 0)
  98 #define PAD_CTL_DSE7            (0x7 << 0)
  99
 100 #define PAD_CTL_FSEL0           (0x0 << 3)
 101 #define PAD_CTL_FSEL1           (0x1 << 3)
 102 #define PAD_CTL_FSEL2           (0x2 << 3)
 103 #define PAD_CTL_FSEL3           (0x3 << 3)
 104
 105 #define PAD_CTL_ODE             (0x1 << 5)
 106 #define PAD_CTL_PUE             (0x1 << 6)
 107 #define PAD_CTL_HYS             (0x1 << 7)
 108 #define PAD_CTL_LVTTL           (0x1 << 8)
 109
 110 #elif defined CONFIG_MX7
 111
 112 #define IOMUX_LPSR_SEL_INPUT_OFS 0x70000
 113
 114 #define PAD_CTL_DSE_1P8V_140OHM   (0x0<<0)
 115 #define PAD_CTL_DSE_1P8V_35OHM    (0x1<<0)
 116 #define PAD_CTL_DSE_1P8V_70OHM    (0x2<<0)
 117 #define PAD_CTL_DSE_1P8V_23OHM    (0x3<<0)
 118
 119 #define PAD_CTL_DSE_3P3V_196OHM   (0x0<<0)
 120 #define PAD_CTL_DSE_3P3V_49OHM    (0x1<<0)
 121 #define PAD_CTL_DSE_3P3V_98OHM    (0x2<<0)
 122 #define PAD_CTL_DSE_3P3V_32OHM    (0x3<<0)
 123
 124 #define PAD_CTL_SRE_FAST     (0 << 2)
 125 #define PAD_CTL_SRE_SLOW     (0x1 << 2)
 126
 127 #define PAD_CTL_HYS       (0x1 << 3)
 128 #define PAD_CTL_PUE       (0x1 << 4)
 129
 130 #define PAD_CTL_PUS_PD100KOHM  ((0x0 << 5) | PAD_CTL_PUE)
 131 #define PAD_CTL_PUS_PU5KOHM    ((0x1 << 5) | PAD_CTL_PUE)
 132 #define PAD_CTL_PUS_PU47KOHM   ((0x2 << 5) | PAD_CTL_PUE)
 133 #define PAD_CTL_PUS_PU100KOHM  ((0x3 << 5) | PAD_CTL_PUE)
 134
 135 #else
 136
 137 #ifdef CONFIG_MX6
 138
 139 #define PAD_CTL_HYS             (1 << 16)
 140
 141 #define PAD_CTL_PUS_100K_DOWN   (0 << 14 | PAD_CTL_PUE)
 142 #define PAD_CTL_PUS_47K_UP      (1 << 14 | PAD_CTL_PUE)
 143 #define PAD_CTL_PUS_100K_UP     (2 << 14 | PAD_CTL_PUE)
 144 #define PAD_CTL_PUS_22K_UP      (3 << 14 | PAD_CTL_PUE)
 145 #define PAD_CTL_PUE             (1 << 13 | PAD_CTL_PKE)
 146 #define PAD_CTL_PKE             (1 << 12)
 147
 148 #define PAD_CTL_ODE             (1 << 11)
 149
 150 #if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
 151 #define PAD_CTL_SPEED_LOW       (0 << 6)
 152 #else
 153 #define PAD_CTL_SPEED_LOW       (1 << 6)
 154 #endif
 155 #define PAD_CTL_SPEED_MED       (2 << 6)
 156 #define PAD_CTL_SPEED_HIGH      (3 << 6)
 157
 158 #define PAD_CTL_DSE_DISABLE     (0 << 3)
 159 #define PAD_CTL_DSE_240ohm      (1 << 3)
 160 #define PAD_CTL_DSE_120ohm      (2 << 3)
 161 #define PAD_CTL_DSE_80ohm       (3 << 3)
 162 #define PAD_CTL_DSE_60ohm       (4 << 3)
 163 #define PAD_CTL_DSE_48ohm       (5 << 3)
 164 #define PAD_CTL_DSE_40ohm       (6 << 3)
 165 #define PAD_CTL_DSE_34ohm       (7 << 3)
 166
 167 /* i.MX6SL/SLL */
 168 #define PAD_CTL_LVE             (1 << 1)
 169 #define PAD_CTL_LVE_BIT         (1 << 22)
 170
 171 /* i.MX6SLL */
 172 #define PAD_CTL_IPD_BIT         (1 << 27)
 173
 174 #elif defined(CONFIG_VF610)
 175
 176 #define PAD_MUX_MODE_SHIFT      20
 177
 178 #define PAD_CTL_INPUT_DIFFERENTIAL (1 << 16)
 179
 180 #define PAD_CTL_SPEED_MED       (1 << 12)
 181 #define PAD_CTL_SPEED_HIGH      (3 << 12)
 182
 183 #define PAD_CTL_SRE             (1 << 11)
 184
 185 #define PAD_CTL_ODE             (1 << 10)
 186
 187 #define PAD_CTL_DSE_150ohm      (1 << 6)
 188 #define PAD_CTL_DSE_75ohm       (2 << 6)
 189 #define PAD_CTL_DSE_50ohm       (3 << 6)
 190 #define PAD_CTL_DSE_37ohm       (4 << 6)
 191 #define PAD_CTL_DSE_30ohm       (5 << 6)
 192 #define PAD_CTL_DSE_25ohm       (6 << 6)
 193 #define PAD_CTL_DSE_20ohm       (7 << 6)
 194
 195 #define PAD_CTL_PUS_47K_UP      (1 << 4 | PAD_CTL_PUE)
 196 #define PAD_CTL_PUS_100K_UP     (2 << 4 | PAD_CTL_PUE)
 197 #define PAD_CTL_PUS_22K_UP      (3 << 4 | PAD_CTL_PUE)
 198 #define PAD_CTL_PKE             (1 << 3)
 199 #define PAD_CTL_PUE             (1 << 2 | PAD_CTL_PKE)
 200
 201 #define PAD_CTL_OBE_IBE_ENABLE  (3 << 0)
 202 #define PAD_CTL_OBE_ENABLE      (1 << 1)
 203 #define PAD_CTL_IBE_ENABLE      (1 << 0)
 204
 205 #else
 206
 207 #define PAD_CTL_DVS             (1 << 13)
 208 #define PAD_CTL_INPUT_DDR       (1 << 9)
 209 #define PAD_CTL_HYS             (1 << 8)
 210
 211 #define PAD_CTL_PKE             (1 << 7)
 212 #define PAD_CTL_PUE             (1 << 6 | PAD_CTL_PKE)
 213 #define PAD_CTL_PUS_100K_DOWN   (0 << 4 | PAD_CTL_PUE)
 214 #define PAD_CTL_PUS_47K_UP      (1 << 4 | PAD_CTL_PUE)
 215 #define PAD_CTL_PUS_100K_UP     (2 << 4 | PAD_CTL_PUE)
 216 #define PAD_CTL_PUS_22K_UP      (3 << 4 | PAD_CTL_PUE)
 217
 218 #define PAD_CTL_ODE             (1 << 3)
 219
 220 #define PAD_CTL_DSE_LOW         (0 << 1)
 221 #define PAD_CTL_DSE_MED         (1 << 1)
 222 #define PAD_CTL_DSE_HIGH        (2 << 1)
 223 #define PAD_CTL_DSE_MAX         (3 << 1)
 224
 225 #endif
 226
 227 #define PAD_CTL_SRE_SLOW        (0 << 0)
 228 #define PAD_CTL_SRE_FAST        (1 << 0)
 229
 230 #endif
 231
 232 #define IOMUX_CONFIG_SION       0x10
 233
 234 #define GPIO_PIN_MASK           0x1f
 235 #define GPIO_PORT_SHIFT         5
 236 #define GPIO_PORT_MASK          (0x7 << GPIO_PORT_SHIFT)
 237 #define GPIO_PORTA              (0 << GPIO_PORT_SHIFT)
 238 #define GPIO_PORTB              (1 << GPIO_PORT_SHIFT)
 239 #define GPIO_PORTC              (2 << GPIO_PORT_SHIFT)
 240 #define GPIO_PORTD              (3 << GPIO_PORT_SHIFT)
 241 #define GPIO_PORTE              (4 << GPIO_PORT_SHIFT)
 242 #define GPIO_PORTF              (5 << GPIO_PORT_SHIFT)
 243
 244 void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
 245 void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
 246                                      unsigned count);
 247 /*
 248 * Set bits for general purpose registers
 249 */
 250 void imx_iomux_set_gpr_register(int group, int start_bit,
 251                                          int num_bits, int value);
 252 #ifdef CONFIG_IOMUX_SHARE_CONF_REG
 253 void imx_iomux_gpio_set_direction(unsigned int gpio,
 254                                 unsigned int direction);
 255 void imx_iomux_gpio_get_function(unsigned int gpio,
 256                                 u32 *gpio_state);
 257 #endif
 258
 259 /* macros for declaring and using pinmux array */
 260 #if defined(CONFIG_MX6QDL)
 261 #define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
 262 #define SETUP_IOMUX_PAD(def)                                    \
 263 if (is_mx6dq() || is_mx6dqp()) {                                \
 264         imx_iomux_v3_setup_pad(MX6Q_##def);                     \
 265 } else {                                                        \
 266         imx_iomux_v3_setup_pad(MX6DL_##def);                    \
 267 }
 268 #define SETUP_IOMUX_PADS(x)                                     \
 269         imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2)
 270 #elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
 271 #define IOMUX_PADS(x) MX6Q_##x
 272 #define SETUP_IOMUX_PAD(def)                                    \
 273         imx_iomux_v3_setup_pad(MX6Q_##def);
 274 #define SETUP_IOMUX_PADS(x)                                     \
 275         imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
 276 #elif defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
 277 #define IOMUX_PADS(x) MX6_##x
 278 #define SETUP_IOMUX_PAD(def)                                    \
 279         imx_iomux_v3_setup_pad(MX6_##def);
 280 #define SETUP_IOMUX_PADS(x)                                     \
 281         imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
 282 #else
 283 #define IOMUX_PADS(x) MX6DL_##x
 284 #define SETUP_IOMUX_PAD(def)                                    \
 285         imx_iomux_v3_setup_pad(MX6DL_##def);
 286 #define SETUP_IOMUX_PADS(x)                                     \
 287         imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
 288 #endif
 289
 290 #endif  /* __MACH_IOMUX_V3_H__*/