arch/arm/include/asm/omap_mmc.h

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Syed Mohammed Khasim <khasim@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef OMAP_MMC_H_
  26 #define OMAP_MMC_H_
  27
  28 #include <mmc.h>
  29
  30 struct hsmmc {
  31 #ifndef CONFIG_OMAP34XX
  32         unsigned int hl_rev;
  33         unsigned int hl_hwinfo;
  34         unsigned int hl_sysconfig;
  35         unsigned char res0[0xf4];
  36 #endif
  37         unsigned char res1[0x10];
  38         unsigned int sysconfig;         /* 0x10 */
  39         unsigned int sysstatus;         /* 0x14 */
  40         unsigned char res2[0x14];
  41         unsigned int con;               /* 0x2C */
  42         unsigned char res3[0xD4];
  43         unsigned int blk;               /* 0x104 */
  44         unsigned int arg;               /* 0x108 */
  45         unsigned int cmd;               /* 0x10C */
  46         unsigned int rsp10;             /* 0x110 */
  47         unsigned int rsp32;             /* 0x114 */
  48         unsigned int rsp54;             /* 0x118 */
  49         unsigned int rsp76;             /* 0x11C */
  50         unsigned int data;              /* 0x120 */
  51         unsigned int pstate;            /* 0x124 */
  52         unsigned int hctl;              /* 0x128 */
  53         unsigned int sysctl;            /* 0x12C */
  54         unsigned int stat;              /* 0x130 */
  55         unsigned int ie;                /* 0x134 */
  56         unsigned char res4[0x4];
  57         unsigned int ac12;              /* 0x13C */
  58         unsigned int capa;              /* 0x140 */
  59         unsigned char res5[0x10];
  60         unsigned int admaes;            /* 0x154 */
  61         unsigned int admasal;           /* 0x158 */
  62 };
  63
  64 struct omap_hsmmc_plat {
  65         struct mmc_config cfg;
  66         struct hsmmc *base_addr;
  67         struct mmc mmc;
  68         bool cd_inverted;
  69         u32 controller_flags;
  70 };
  71
  72 /*
  73  * OMAP HS MMC Bit definitions
  74  */
  75 #define MADMA_EN                        (0x1 << 0)
  76 #define MMC_SOFTRESET                   (0x1 << 1)
  77 #define RESETDONE                       (0x1 << 0)
  78 #define NOOPENDRAIN                     (0x0 << 0)
  79 #define OPENDRAIN                       (0x1 << 0)
  80 #define OD                              (0x1 << 0)
  81 #define INIT_NOINIT                     (0x0 << 1)
  82 #define INIT_INITSTREAM                 (0x1 << 1)
  83 #define HR_NOHOSTRESP                   (0x0 << 2)
  84 #define STR_BLOCK                       (0x0 << 3)
  85 #define MODE_FUNC                       (0x0 << 4)
  86 #define DW8_1_4BITMODE                  (0x0 << 5)
  87 #define MIT_CTO                         (0x0 << 6)
  88 #define CDP_ACTIVEHIGH                  (0x0 << 7)
  89 #define WPP_ACTIVEHIGH                  (0x0 << 8)
  90 #define RESERVED_MASK                   (0x3 << 9)
  91 #define CTPL_MMC_SD                     (0x0 << 11)
  92 #define DDR                             (0x1 << 19)
  93 #define DMA_MASTER                      (0x1 << 20)
  94 #define BLEN_512BYTESLEN                (0x200 << 0)
  95 #define NBLK_STPCNT                     (0x0 << 16)
  96 #define DE_ENABLE                       (0x1 << 0)
  97 #define BCE_ENABLE                      (0x1 << 1)
  98 #define ACEN_ENABLE                     (0x1 << 2)
  99 #define DDIR_OFFSET                     (4)
 100 #define DDIR_MASK                       (0x1 << 4)
 101 #define DDIR_WRITE                      (0x0 << 4)
 102 #define DDIR_READ                       (0x1 << 4)
 103 #define MSBS_SGLEBLK                    (0x0 << 5)
 104 #define MSBS_MULTIBLK                   (0x1 << 5)
 105 #define RSP_TYPE_OFFSET                 (16)
 106 #define RSP_TYPE_MASK                   (0x3 << 16)
 107 #define RSP_TYPE_NORSP                  (0x0 << 16)
 108 #define RSP_TYPE_LGHT136                (0x1 << 16)
 109 #define RSP_TYPE_LGHT48                 (0x2 << 16)
 110 #define RSP_TYPE_LGHT48B                (0x3 << 16)
 111 #define CCCE_NOCHECK                    (0x0 << 19)
 112 #define CCCE_CHECK                      (0x1 << 19)
 113 #define CICE_NOCHECK                    (0x0 << 20)
 114 #define CICE_CHECK                      (0x1 << 20)
 115 #define DP_OFFSET                       (21)
 116 #define DP_MASK                         (0x1 << 21)
 117 #define DP_NO_DATA                      (0x0 << 21)
 118 #define DP_DATA                         (0x1 << 21)
 119 #define CMD_TYPE_NORMAL                 (0x0 << 22)
 120 #define INDEX_OFFSET                    (24)
 121 #define INDEX_MASK                      (0x3f << 24)
 122 #define INDEX(i)                        (i << 24)
 123 #define DATI_MASK                       (0x1 << 1)
 124 #define CMDI_MASK                       (0x1 << 0)
 125 #define DTW_1_BITMODE                   (0x0 << 1)
 126 #define DTW_4_BITMODE                   (0x1 << 1)
 127 #define DTW_8_BITMODE                   (0x1 << 5) /* CON[DW8]*/
 128 #define SDBP_PWROFF                     (0x0 << 8)
 129 #define SDBP_PWRON                      (0x1 << 8)
 130 #define SDVS_MASK                       (0x7 << 9)
 131 #define SDVS_1V8                        (0x5 << 9)
 132 #define SDVS_3V0                        (0x6 << 9)
 133 #define SDVS_3V3                        (0x7 << 9)
 134 #define DMA_SELECT                      (0x2 << 3)
 135 #define ICE_MASK                        (0x1 << 0)
 136 #define ICE_STOP                        (0x0 << 0)
 137 #define ICS_MASK                        (0x1 << 1)
 138 #define ICS_NOTREADY                    (0x0 << 1)
 139 #define ICE_OSCILLATE                   (0x1 << 0)
 140 #define CEN_MASK                        (0x1 << 2)
 141 #define CEN_ENABLE                      (0x1 << 2)
 142 #define CLKD_OFFSET                     (6)
 143 #define CLKD_MASK                       (0x3FF << 6)
 144 #define DTO_MASK                        (0xF << 16)
 145 #define DTO_15THDTO                     (0xE << 16)
 146 #define SOFTRESETALL                    (0x1 << 24)
 147 #define CC_MASK                         (0x1 << 0)
 148 #define TC_MASK                         (0x1 << 1)
 149 #define BWR_MASK                        (0x1 << 4)
 150 #define BRR_MASK                        (0x1 << 5)
 151 #define ERRI_MASK                       (0x1 << 15)
 152 #define IE_CC                           (0x01 << 0)
 153 #define IE_TC                           (0x01 << 1)
 154 #define IE_BWR                          (0x01 << 4)
 155 #define IE_BRR                          (0x01 << 5)
 156 #define IE_CTO                          (0x01 << 16)
 157 #define IE_CCRC                         (0x01 << 17)
 158 #define IE_CEB                          (0x01 << 18)
 159 #define IE_CIE                          (0x01 << 19)
 160 #define IE_DTO                          (0x01 << 20)
 161 #define IE_DCRC                         (0x01 << 21)
 162 #define IE_DEB                          (0x01 << 22)
 163 #define IE_ADMAE                        (0x01 << 25)
 164 #define IE_CERR                         (0x01 << 28)
 165 #define IE_BADA                         (0x01 << 29)
 166
 167 #define VS33_3V3SUP                     BIT(24)
 168 #define VS30_3V0SUP                     BIT(25)
 169 #define VS18_1V8SUP                     BIT(26)
 170
 171 #define IOV_3V3                         3300000
 172 #define IOV_3V0                         3000000
 173 #define IOV_1V8                         1800000
 174
 175 #define AC12_ET                         BIT(22)
 176 #define AC12_UHSMC_MASK                 (7 << 16)
 177 #define AC12_UHSMC_DDR50                (4 << 16)
 178 #define AC12_UHSMC_SDR104               (3 << 16)
 179 #define AC12_UHSMC_SDR50                (2 << 16)
 180 #define AC12_UHSMC_SDR25                (1 << 16)
 181 #define AC12_UHSMC_SDR12                (0 << 16)
 182 #define AC12_UHSMC_RES                  (0x7 << 16)
 183
 184 /* Driver definitions */
 185 #define MMCSD_SECTOR_SIZE               512
 186 #define MMC_CARD                        0
 187 #define SD_CARD                         1
 188 #define BYTE_MODE                       0
 189 #define SECTOR_MODE                     1
 190 #define CLK_INITSEQ                     0
 191 #define CLK_400KHZ                      1
 192 #define CLK_MISC                        2
 193
 194 #define CLKD_MAX                        0x3FF   /* max clock divisor: 1023 */
 195
 196 #define RSP_TYPE_NONE   (RSP_TYPE_NORSP   | CCCE_NOCHECK | CICE_NOCHECK)
 197 #define MMC_CMD0        (INDEX(0)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
 198
 199 /* Clock Configurations and Macros */
 200 #define MMC_CLOCK_REFERENCE     96 /* MHz */
 201
 202 #define mmc_reg_out(addr, mask, val)\
 203         writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
 204
 205 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 206                 int wp_gpio);
 207
 208 void vmmc_pbias_config(uint voltage);
 209 void board_mmc_poweron_ldo(uint voltage);
 210 #endif /* OMAP_MMC_H_ */