arch/arm/include/asm/omap_mmc.h

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Syed Mohammed Khasim <khasim@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef OMAP_MMC_H_
  26 #define OMAP_MMC_H_
  27
  28 struct hsmmc {
  29         unsigned char res1[0x10];
  30         unsigned int sysconfig;         /* 0x10 */
  31         unsigned int sysstatus;         /* 0x14 */
  32         unsigned char res2[0x14];
  33         unsigned int con;               /* 0x2C */
  34         unsigned char res3[0xD4];
  35         unsigned int blk;               /* 0x104 */
  36         unsigned int arg;               /* 0x108 */
  37         unsigned int cmd;               /* 0x10C */
  38         unsigned int rsp10;             /* 0x110 */
  39         unsigned int rsp32;             /* 0x114 */
  40         unsigned int rsp54;             /* 0x118 */
  41         unsigned int rsp76;             /* 0x11C */
  42         unsigned int data;              /* 0x120 */
  43         unsigned int pstate;            /* 0x124 */
  44         unsigned int hctl;              /* 0x128 */
  45         unsigned int sysctl;            /* 0x12C */
  46         unsigned int stat;              /* 0x130 */
  47         unsigned int ie;                /* 0x134 */
  48         unsigned char res4[0x8];
  49         unsigned int capa;              /* 0x140 */
  50 };
  51
  52 /*
  53  * OMAP HS MMC Bit definitions
  54  */
  55 #define MMC_SOFTRESET                   (0x1 << 1)
  56 #define RESETDONE                       (0x1 << 0)
  57 #define NOOPENDRAIN                     (0x0 << 0)
  58 #define OPENDRAIN                       (0x1 << 0)
  59 #define OD                              (0x1 << 0)
  60 #define INIT_NOINIT                     (0x0 << 1)
  61 #define INIT_INITSTREAM                 (0x1 << 1)
  62 #define HR_NOHOSTRESP                   (0x0 << 2)
  63 #define STR_BLOCK                       (0x0 << 3)
  64 #define MODE_FUNC                       (0x0 << 4)
  65 #define DW8_1_4BITMODE                  (0x0 << 5)
  66 #define MIT_CTO                         (0x0 << 6)
  67 #define CDP_ACTIVEHIGH                  (0x0 << 7)
  68 #define WPP_ACTIVEHIGH                  (0x0 << 8)
  69 #define RESERVED_MASK                   (0x3 << 9)
  70 #define CTPL_MMC_SD                     (0x0 << 11)
  71 #define BLEN_512BYTESLEN                (0x200 << 0)
  72 #define NBLK_STPCNT                     (0x0 << 16)
  73 #define DE_DISABLE                      (0x0 << 0)
  74 #define BCE_DISABLE                     (0x0 << 1)
  75 #define BCE_ENABLE                      (0x1 << 1)
  76 #define ACEN_DISABLE                    (0x0 << 2)
  77 #define DDIR_OFFSET                     (4)
  78 #define DDIR_MASK                       (0x1 << 4)
  79 #define DDIR_WRITE                      (0x0 << 4)
  80 #define DDIR_READ                       (0x1 << 4)
  81 #define MSBS_SGLEBLK                    (0x0 << 5)
  82 #define MSBS_MULTIBLK                   (0x1 << 5)
  83 #define RSP_TYPE_OFFSET                 (16)
  84 #define RSP_TYPE_MASK                   (0x3 << 16)
  85 #define RSP_TYPE_NORSP                  (0x0 << 16)
  86 #define RSP_TYPE_LGHT136                (0x1 << 16)
  87 #define RSP_TYPE_LGHT48                 (0x2 << 16)
  88 #define RSP_TYPE_LGHT48B                (0x3 << 16)
  89 #define CCCE_NOCHECK                    (0x0 << 19)
  90 #define CCCE_CHECK                      (0x1 << 19)
  91 #define CICE_NOCHECK                    (0x0 << 20)
  92 #define CICE_CHECK                      (0x1 << 20)
  93 #define DP_OFFSET                       (21)
  94 #define DP_MASK                         (0x1 << 21)
  95 #define DP_NO_DATA                      (0x0 << 21)
  96 #define DP_DATA                         (0x1 << 21)
  97 #define CMD_TYPE_NORMAL                 (0x0 << 22)
  98 #define INDEX_OFFSET                    (24)
  99 #define INDEX_MASK                      (0x3f << 24)
 100 #define INDEX(i)                        (i << 24)
 101 #define DATI_MASK                       (0x1 << 1)
 102 #define CMDI_MASK                       (0x1 << 0)
 103 #define DTW_1_BITMODE                   (0x0 << 1)
 104 #define DTW_4_BITMODE                   (0x1 << 1)
 105 #define DTW_8_BITMODE                   (0x1 << 5) /* CON[DW8]*/
 106 #define SDBP_PWROFF                     (0x0 << 8)
 107 #define SDBP_PWRON                      (0x1 << 8)
 108 #define SDVS_1V8                        (0x5 << 9)
 109 #define SDVS_3V0                        (0x6 << 9)
 110 #define ICE_MASK                        (0x1 << 0)
 111 #define ICE_STOP                        (0x0 << 0)
 112 #define ICS_MASK                        (0x1 << 1)
 113 #define ICS_NOTREADY                    (0x0 << 1)
 114 #define ICE_OSCILLATE                   (0x1 << 0)
 115 #define CEN_MASK                        (0x1 << 2)
 116 #define CEN_DISABLE                     (0x0 << 2)
 117 #define CEN_ENABLE                      (0x1 << 2)
 118 #define CLKD_OFFSET                     (6)
 119 #define CLKD_MASK                       (0x3FF << 6)
 120 #define DTO_MASK                        (0xF << 16)
 121 #define DTO_15THDTO                     (0xE << 16)
 122 #define SOFTRESETALL                    (0x1 << 24)
 123 #define CC_MASK                         (0x1 << 0)
 124 #define TC_MASK                         (0x1 << 1)
 125 #define BWR_MASK                        (0x1 << 4)
 126 #define BRR_MASK                        (0x1 << 5)
 127 #define ERRI_MASK                       (0x1 << 15)
 128 #define IE_CC                           (0x01 << 0)
 129 #define IE_TC                           (0x01 << 1)
 130 #define IE_BWR                          (0x01 << 4)
 131 #define IE_BRR                          (0x01 << 5)
 132 #define IE_CTO                          (0x01 << 16)
 133 #define IE_CCRC                         (0x01 << 17)
 134 #define IE_CEB                          (0x01 << 18)
 135 #define IE_CIE                          (0x01 << 19)
 136 #define IE_DTO                          (0x01 << 20)
 137 #define IE_DCRC                         (0x01 << 21)
 138 #define IE_DEB                          (0x01 << 22)
 139 #define IE_CERR                         (0x01 << 28)
 140 #define IE_BADA                         (0x01 << 29)
 141
 142 #define VS30_3V0SUP                     (1 << 25)
 143 #define VS18_1V8SUP                     (1 << 26)
 144
 145 /* Driver definitions */
 146 #define MMCSD_SECTOR_SIZE               512
 147 #define MMC_CARD                        0
 148 #define SD_CARD                         1
 149 #define BYTE_MODE                       0
 150 #define SECTOR_MODE                     1
 151 #define CLK_INITSEQ                     0
 152 #define CLK_400KHZ                      1
 153 #define CLK_MISC                        2
 154
 155 #define RSP_TYPE_NONE   (RSP_TYPE_NORSP   | CCCE_NOCHECK | CICE_NOCHECK)
 156 #define MMC_CMD0        (INDEX(0)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
 157
 158 /* Clock Configurations and Macros */
 159 #define MMC_CLOCK_REFERENCE     96 /* MHz */
 160
 161 #define mmc_reg_out(addr, mask, val)\
 162         writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
 163
 164 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
 165                 int wp_gpio);
 166
 167
 168 #endif /* OMAP_MMC_H_ */