2 * SoC-specific lowlevel code for DA850
5 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/da850_lowlevel.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/davinci_misc.h>
16 #include <asm/arch/ddr2_defs.h>
17 #include <asm/ti-common/davinci_nand.h>
18 #include <asm/arch/pll_defs.h>
20 void davinci_enable_uart0(void)
22 lpsc_on(DAVINCI_LPSC_UART0
);
24 /* Bringup UART0 out of reset */
25 REG(UART0_PWREMU_MGMT
) = 0x00006001;
28 #if defined(CONFIG_SYS_DA850_PLL_INIT)
29 static void da850_waitloop(unsigned long loopcnt
)
33 for (i
= 0; i
< loopcnt
; i
++)
37 static int da850_pll_init(struct davinci_pllc_regs
*reg
, unsigned long pllmult
)
39 if (reg
== davinci_pllc0_regs
)
40 /* Unlock PLL registers. */
41 clrbits_le32(&davinci_syscfg_regs
->cfgchip0
, PLL_MASTER_LOCK
);
44 * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
47 clrbits_le32(®
->pllctl
, PLLCTL_PLLENSRC
);
48 /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
49 clrbits_le32(®
->pllctl
, PLLCTL_EXTCLKSRC
);
51 /* Set PLLEN=0 => PLL BYPASS MODE */
52 clrbits_le32(®
->pllctl
, PLLCTL_PLLEN
);
56 if (reg
== davinci_pllc0_regs
) {
58 * Select the Clock Mode bit 8 as External Clock or On Chip
61 dv_maskbits(®
->pllctl
, ~PLLCTL_RES_9
);
62 setbits_le32(®
->pllctl
,
63 (CONFIG_SYS_DV_CLKMODE
<< PLLCTL_CLOCK_MODE_SHIFT
));
66 /* Clear PLLRST bit to reset the PLL */
67 clrbits_le32(®
->pllctl
, PLLCTL_PLLRST
);
69 /* Disable the PLL output */
70 setbits_le32(®
->pllctl
, PLLCTL_PLLDIS
);
72 /* PLL initialization sequence */
74 * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
77 clrbits_le32(®
->pllctl
, PLLCTL_PLLPWRDN
);
79 /* Enable the PLL from Disable Mode PLLDIS bit to 0 */
80 clrbits_le32(®
->pllctl
, PLLCTL_PLLDIS
);
82 #if defined(CONFIG_SYS_DA850_PLL0_PREDIV)
83 /* program the prediv */
84 if (reg
== davinci_pllc0_regs
&& CONFIG_SYS_DA850_PLL0_PREDIV
)
85 writel((PLL_DIVEN
| CONFIG_SYS_DA850_PLL0_PREDIV
),
89 /* Program the required multiplier value in PLLM */
90 writel(pllmult
, ®
->pllm
);
92 /* program the postdiv */
93 if (reg
== davinci_pllc0_regs
)
94 writel((PLL_POSTDEN
| CONFIG_SYS_DA850_PLL0_POSTDIV
),
97 writel((PLL_POSTDEN
| CONFIG_SYS_DA850_PLL1_POSTDIV
),
101 * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
102 * no GO operation is currently in progress
104 while ((readl(®
->pllstat
) & PLLCMD_GOSTAT
) == PLLCMD_GOSTAT
)
107 if (reg
== davinci_pllc0_regs
) {
108 writel(CONFIG_SYS_DA850_PLL0_PLLDIV1
, ®
->plldiv1
);
109 writel(CONFIG_SYS_DA850_PLL0_PLLDIV2
, ®
->plldiv2
);
110 writel(CONFIG_SYS_DA850_PLL0_PLLDIV3
, ®
->plldiv3
);
111 writel(CONFIG_SYS_DA850_PLL0_PLLDIV4
, ®
->plldiv4
);
112 writel(CONFIG_SYS_DA850_PLL0_PLLDIV5
, ®
->plldiv5
);
113 writel(CONFIG_SYS_DA850_PLL0_PLLDIV6
, ®
->plldiv6
);
114 writel(CONFIG_SYS_DA850_PLL0_PLLDIV7
, ®
->plldiv7
);
116 writel(CONFIG_SYS_DA850_PLL1_PLLDIV1
, ®
->plldiv1
);
117 writel(CONFIG_SYS_DA850_PLL1_PLLDIV2
, ®
->plldiv2
);
118 writel(CONFIG_SYS_DA850_PLL1_PLLDIV3
, ®
->plldiv3
);
122 * Set the GOSET bit in PLLCMD to 1 to initiate a new divider
125 setbits_le32(®
->pllcmd
, PLLCMD_GOSTAT
);
128 * Wait for the GOSTAT bit in PLLSTAT to clear to 0
129 * (completion of phase alignment).
131 while ((readl(®
->pllstat
) & PLLCMD_GOSTAT
) == PLLCMD_GOSTAT
)
134 /* Wait for PLL to reset properly. See PLL spec for PLL reset time */
137 /* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
138 setbits_le32(®
->pllctl
, PLLCTL_PLLRST
);
140 /* Wait for PLL to lock. See PLL spec for PLL lock time */
141 da850_waitloop(2400);
144 * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
147 setbits_le32(®
->pllctl
, PLLCTL_PLLEN
);
151 * clear EMIFA and EMIFB clock source settings, let them
154 if (reg
== davinci_pllc0_regs
)
155 dv_maskbits(&davinci_syscfg_regs
->cfgchip3
,
156 ~(PLL_SCSCFG3_DIV45PENA
| PLL_SCSCFG3_EMA_CLKSRC
));
160 #endif /* CONFIG_SYS_DA850_PLL_INIT */
162 #if defined(CONFIG_SYS_DA850_DDR_INIT)
163 static int da850_ddr_setup(void)
167 /* Enable the Clock to DDR2/mDDR */
168 lpsc_on(DAVINCI_LPSC_DDR_EMIF
);
170 tmp
= readl(&davinci_syscfg1_regs
->vtpio_ctl
);
171 if ((tmp
& VTP_POWERDWN
) == VTP_POWERDWN
) {
172 /* Begin VTP Calibration */
173 clrbits_le32(&davinci_syscfg1_regs
->vtpio_ctl
, VTP_POWERDWN
);
174 clrbits_le32(&davinci_syscfg1_regs
->vtpio_ctl
, VTP_LOCK
);
175 setbits_le32(&davinci_syscfg1_regs
->vtpio_ctl
, VTP_CLKRZ
);
176 clrbits_le32(&davinci_syscfg1_regs
->vtpio_ctl
, VTP_CLKRZ
);
177 setbits_le32(&davinci_syscfg1_regs
->vtpio_ctl
, VTP_CLKRZ
);
179 /* Polling READY bit to see when VTP calibration is done */
180 tmp
= readl(&davinci_syscfg1_regs
->vtpio_ctl
);
181 while ((tmp
& VTP_READY
) != VTP_READY
)
182 tmp
= readl(&davinci_syscfg1_regs
->vtpio_ctl
);
184 setbits_le32(&davinci_syscfg1_regs
->vtpio_ctl
, VTP_LOCK
);
185 setbits_le32(&davinci_syscfg1_regs
->vtpio_ctl
, VTP_POWERDWN
);
187 setbits_le32(&davinci_syscfg1_regs
->vtpio_ctl
, VTP_IOPWRDWN
);
188 writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR
, &dv_ddr2_regs_ctrl
->ddrphycr
);
190 if (CONFIG_SYS_DA850_DDR2_SDBCR
& (1 << DV_DDR_SDCR_DDR2EN_SHIFT
)) {
192 clrbits_le32(&davinci_syscfg1_regs
->ddr_slew
,
193 (1 << DDR_SLEW_DDR_PDENA_BIT
) |
194 (1 << DDR_SLEW_CMOSEN_BIT
));
197 setbits_le32(&davinci_syscfg1_regs
->ddr_slew
,
198 (1 << DDR_SLEW_DDR_PDENA_BIT
) |
199 (1 << DDR_SLEW_CMOSEN_BIT
));
203 * SDRAM Configuration Register (SDCR):
204 * First set the BOOTUNLOCK bit to make configuration bits
207 setbits_le32(&dv_ddr2_regs_ctrl
->sdbcr
, DV_DDR_BOOTUNLOCK
);
210 * Write the new value of these bits and clear BOOTUNLOCK.
211 * At the same time, set the TIMUNLOCK bit to allow changing
212 * the timing registers
214 tmp
= CONFIG_SYS_DA850_DDR2_SDBCR
;
215 tmp
&= ~DV_DDR_BOOTUNLOCK
;
216 tmp
|= DV_DDR_TIMUNLOCK
;
217 writel(tmp
, &dv_ddr2_regs_ctrl
->sdbcr
);
219 /* write memory configuration and timing */
220 if (!(CONFIG_SYS_DA850_DDR2_SDBCR
& (1 << DV_DDR_SDCR_DDR2EN_SHIFT
))) {
222 writel(CONFIG_SYS_DA850_DDR2_SDBCR2
,
223 &dv_ddr2_regs_ctrl
->sdbcr2
);
225 writel(CONFIG_SYS_DA850_DDR2_SDTIMR
, &dv_ddr2_regs_ctrl
->sdtimr
);
226 writel(CONFIG_SYS_DA850_DDR2_SDTIMR2
, &dv_ddr2_regs_ctrl
->sdtimr2
);
228 /* clear the TIMUNLOCK bit and write the value of the CL field */
229 tmp
&= ~DV_DDR_TIMUNLOCK
;
230 writel(tmp
, &dv_ddr2_regs_ctrl
->sdbcr
);
233 * LPMODEN and MCLKSTOPEN must be set!
234 * Without this bits set, PSC don;t switch states !!
236 writel(CONFIG_SYS_DA850_DDR2_SDRCR
|
237 (1 << DV_DDR_SRCR_LPMODEN_SHIFT
) |
238 (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT
),
239 &dv_ddr2_regs_ctrl
->sdrcr
);
241 /* SyncReset the Clock to EMIF3A SDRAM */
242 lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF
);
243 /* Enable the Clock to EMIF3A SDRAM */
244 lpsc_on(DAVINCI_LPSC_DDR_EMIF
);
246 /* disable self refresh */
247 clrbits_le32(&dv_ddr2_regs_ctrl
->sdrcr
,
248 DV_DDR_SDRCR_LPMODEN
| DV_DDR_SDRCR_MCLKSTOPEN
);
249 writel(CONFIG_SYS_DA850_DDR2_PBBPR
, &dv_ddr2_regs_ctrl
->pbbpr
);
253 #endif /* CONFIG_SYS_DA850_DDR_INIT */
255 __attribute__((weak
))
256 void board_gpio_init(void)
261 int arch_cpu_init(void)
263 /* Unlock kick registers */
264 writel(DV_SYSCFG_KICK0_UNLOCK
, &davinci_syscfg_regs
->kick0
);
265 writel(DV_SYSCFG_KICK1_UNLOCK
, &davinci_syscfg_regs
->kick1
);
267 dv_maskbits(&davinci_syscfg_regs
->suspsrc
,
268 CONFIG_SYS_DA850_SYSCFG_SUSPSRC
);
270 /* configure pinmux settings */
271 if (davinci_configure_pin_mux_items(pinmuxes
, pinmuxes_size
))
274 #if defined(CONFIG_SYS_DA850_PLL_INIT)
276 da850_pll_init(davinci_pllc0_regs
, CONFIG_SYS_DA850_PLL0_PLLM
);
277 da850_pll_init(davinci_pllc1_regs
, CONFIG_SYS_DA850_PLL1_PLLM
);
279 /* setup CSn config */
280 #if defined(CONFIG_SYS_DA850_CS2CFG)
281 writel(CONFIG_SYS_DA850_CS2CFG
, &davinci_emif_regs
->ab1cr
);
283 #if defined(CONFIG_SYS_DA850_CS3CFG)
284 writel(CONFIG_SYS_DA850_CS3CFG
, &davinci_emif_regs
->ab2cr
);
287 da8xx_configure_lpsc_items(lpsc
, lpsc_size
);
293 NS16550_init((NS16550_t
)(CONFIG_SYS_NS16550_COM1
),
294 CONFIG_SYS_NS16550_CLK
/ 16 / CONFIG_BAUDRATE
);
297 * Fix Power and Emulation Management Register
298 * see sprufw3a.pdf page 37 Table 24
300 writel((DAVINCI_UART_PWREMU_MGMT_FREE
| DAVINCI_UART_PWREMU_MGMT_URRST
|
301 DAVINCI_UART_PWREMU_MGMT_UTRST
),
302 #if (CONFIG_SYS_NS16550_COM1 == DAVINCI_UART0_BASE)
303 &davinci_uart0_ctrl_regs
->pwremu_mgmt
);
305 &davinci_uart2_ctrl_regs
->pwremu_mgmt
);
308 #if defined(CONFIG_SYS_DA850_DDR_INIT)