]> git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arm/mach-davinci/dm644x.c
ARM: davinci: move SoC sources to mach-davinci
[people/ms/u-boot.git] / arch / arm / mach-davinci / dm644x.c
1 /*
2 * SoC-specific code for tms320dm644x chips
3 *
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
5 * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
6 * Copyright (C) 2004 Texas Instruments.
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 #include <common.h>
12 #include <asm/arch/hardware.h>
13
14
15 #define PINMUX0_EMACEN (1 << 31)
16 #define PINMUX0_AECS5 (1 << 11)
17 #define PINMUX0_AECS4 (1 << 10)
18
19 #define PINMUX1_I2C (1 << 7)
20 #define PINMUX1_UART1 (1 << 1)
21 #define PINMUX1_UART0 (1 << 0)
22
23
24 void davinci_enable_uart0(void)
25 {
26 lpsc_on(DAVINCI_LPSC_UART0);
27
28 /* Bringup UART0 out of reset */
29 REG(UART0_PWREMU_MGMT) = 0x00006001;
30
31 /* Enable UART0 MUX lines */
32 REG(PINMUX1) |= PINMUX1_UART0;
33 }
34
35 #ifdef CONFIG_DRIVER_TI_EMAC
36 void davinci_enable_emac(void)
37 {
38 lpsc_on(DAVINCI_LPSC_EMAC);
39 lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
40 lpsc_on(DAVINCI_LPSC_MDIO);
41
42 /* Enable GIO3.3V cells used for EMAC */
43 REG(VDD3P3V_PWDN) = 0;
44
45 /* Enable EMAC. */
46 REG(PINMUX0) |= PINMUX0_EMACEN;
47 }
48 #endif
49
50 #ifdef CONFIG_SYS_I2C_DAVINCI
51 void davinci_enable_i2c(void)
52 {
53 lpsc_on(DAVINCI_LPSC_I2C);
54
55 /* Enable I2C pin Mux */
56 REG(PINMUX1) |= PINMUX1_I2C;
57 }
58 #endif
59
60 void davinci_errata_workarounds(void)
61 {
62 /*
63 * Workaround for TMS320DM6446 errata 1.3.22:
64 * PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset
65 * Revision(s) Affected: 1.3 and earlier
66 */
67 REG(PSC_SILVER_BULLET) = 0;
68
69 /*
70 * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR)
71 * as suggested in TMS320DM6446 errata 2.1.2:
72 *
73 * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions
74 * low priority modules can occupy the bus and prevent high priority
75 * modules like the VPSS from getting the required DDR2 throughput.
76 * A hex value of 0x20 should provide a good ARM (cache enabled)
77 * performance and still allow good utilization by the VPSS or other
78 * modules.
79 */
80 REG(VBPR) = 0x20;
81 }