arch/arm/mach-imx/init.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <asm/io.h>
   8 #include <asm/arch/imx-regs.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/sys_proto.h>
  11 #include <asm/mach-imx/boot_mode.h>
  12 #include <asm/arch/crm_regs.h>
  13
  14 void init_aips(void)
  15 {
  16         struct aipstz_regs *aips1, *aips2, *aips3;
  17
  18         aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
  19         aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
  20         aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
  21
  22         /*
  23          * Set all MPROTx to be non-bufferable, trusted for R/W,
  24          * not forced to user-mode.
  25          */
  26         writel(0x77777777, &aips1->mprot0);
  27         writel(0x77777777, &aips1->mprot1);
  28         writel(0x77777777, &aips2->mprot0);
  29         writel(0x77777777, &aips2->mprot1);
  30
  31         /*
  32          * Set all OPACRx to be non-bufferable, not require
  33          * supervisor privilege level for access,allow for
  34          * write access and untrusted master access.
  35          */
  36         writel(0x00000000, &aips1->opacr0);
  37         writel(0x00000000, &aips1->opacr1);
  38         writel(0x00000000, &aips1->opacr2);
  39         writel(0x00000000, &aips1->opacr3);
  40         writel(0x00000000, &aips1->opacr4);
  41         writel(0x00000000, &aips2->opacr0);
  42         writel(0x00000000, &aips2->opacr1);
  43         writel(0x00000000, &aips2->opacr2);
  44         writel(0x00000000, &aips2->opacr3);
  45         writel(0x00000000, &aips2->opacr4);
  46
  47         if (is_mx6ull() || is_mx6sx() || is_mx7()) {
  48                 /*
  49                  * Set all MPROTx to be non-bufferable, trusted for R/W,
  50                  * not forced to user-mode.
  51                  */
  52                 writel(0x77777777, &aips3->mprot0);
  53                 writel(0x77777777, &aips3->mprot1);
  54
  55                 /*
  56                  * Set all OPACRx to be non-bufferable, not require
  57                  * supervisor privilege level for access,allow for
  58                  * write access and untrusted master access.
  59                  */
  60                 writel(0x00000000, &aips3->opacr0);
  61                 writel(0x00000000, &aips3->opacr1);
  62                 writel(0x00000000, &aips3->opacr2);
  63                 writel(0x00000000, &aips3->opacr3);
  64                 writel(0x00000000, &aips3->opacr4);
  65         }
  66 }
  67
  68 void imx_set_wdog_powerdown(bool enable)
  69 {
  70         struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
  71         struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
  72         struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
  73 #ifdef CONFIG_MX7D
  74         struct wdog_regs *wdog4 = (struct wdog_regs *)WDOG4_BASE_ADDR;
  75 #endif
  76
  77         /* Write to the PDE (Power Down Enable) bit */
  78         writew(enable, &wdog1->wmcr);
  79         writew(enable, &wdog2->wmcr);
  80
  81         if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx7())
  82                 writew(enable, &wdog3->wmcr);
  83 #ifdef CONFIG_MX7D
  84         writew(enable, &wdog4->wmcr);
  85 #endif
  86 }
  87
  88 #define SRC_SCR_WARM_RESET_ENABLE       0
  89
  90 void init_src(void)
  91 {
  92         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  93         u32 val;
  94
  95         /*
  96          * force warm reset sources to generate cold reset
  97          * for a more reliable restart
  98          */
  99         val = readl(&src_regs->scr);
 100         val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
 101         writel(val, &src_regs->scr);
 102 }
 103
 104 #ifdef CONFIG_CMD_BMODE
 105 void boot_mode_apply(unsigned cfg_val)
 106 {
 107         unsigned reg;
 108         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 109         writel(cfg_val, &psrc->gpr9);
 110         reg = readl(&psrc->gpr10);
 111         if (cfg_val)
 112                 reg |= 1 << 28;
 113         else
 114                 reg &= ~(1 << 28);
 115         writel(reg, &psrc->gpr10);
 116 }
 117 #endif
 118
 119 #if defined(CONFIG_MX6)
 120 u32 imx6_src_get_boot_mode(void)
 121 {
 122         if (imx6_is_bmode_from_gpr9())
 123                 return readl(&src_base->gpr9);
 124         else
 125                 return readl(&src_base->sbmr1);
 126 }
 127 #endif