arch/arm/mach-imx/iomux-v3.c

   1 /*
   2  * Based on the iomux-v3.c from Linux kernel:
   3  * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
   4  * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
   5  *                       <armlinux@phytec.de>
   6  *
   7  * Copyright (C) 2004-2011 Freescale Semiconductor, Inc.
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11 #include <common.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/mach-imx/iomux-v3.h>
  15 #include <asm/mach-imx/sys_proto.h>
  16
  17 static void *base = (void *)IOMUXC_BASE_ADDR;
  18
  19 /*
  20  * configures a single pad in the iomuxer
  21  */
  22 void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
  23 {
  24         u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
  25         u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
  26         u32 sel_input_ofs =
  27                 (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
  28         u32 sel_input =
  29                 (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
  30         u32 pad_ctrl_ofs =
  31                 (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
  32         u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
  33
  34 #if defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
  35         /* Check whether LVE bit needs to be set */
  36         if (pad_ctrl & PAD_CTL_LVE) {
  37                 pad_ctrl &= ~PAD_CTL_LVE;
  38                 pad_ctrl |= PAD_CTL_LVE_BIT;
  39         }
  40 #endif
  41
  42 #ifdef CONFIG_IOMUX_LPSR
  43         u32 lpsr = (pad & MUX_MODE_LPSR) >> MUX_MODE_SHIFT;
  44
  45 #ifdef CONFIG_MX7
  46         if (lpsr == IOMUX_CONFIG_LPSR) {
  47                 base = (void *)IOMUXC_LPSR_BASE_ADDR;
  48                 mux_mode &= ~IOMUX_CONFIG_LPSR;
  49                 /* set daisy chain sel_input */
  50                 if (sel_input_ofs)
  51                         sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS;
  52         }
  53 #else
  54         if (is_mx6ull() || is_mx6sll()) {
  55                 if (lpsr == IOMUX_CONFIG_LPSR) {
  56                         base = (void *)IOMUXC_SNVS_BASE_ADDR;
  57                         mux_mode &= ~IOMUX_CONFIG_LPSR;
  58                 }
  59         }
  60 #endif
  61 #endif
  62
  63         if (is_mx7() || is_mx6ull() || is_mx6sll() || mux_ctrl_ofs)
  64                 __raw_writel(mux_mode, base + mux_ctrl_ofs);
  65
  66         if (sel_input_ofs)
  67                 __raw_writel(sel_input, base + sel_input_ofs);
  68
  69 #ifdef CONFIG_IOMUX_SHARE_CONF_REG
  70         if (!(pad_ctrl & NO_PAD_CTRL))
  71                 __raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl,
  72                         base + pad_ctrl_ofs);
  73 #else
  74         if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
  75                 __raw_writel(pad_ctrl, base + pad_ctrl_ofs);
  76 #if defined(CONFIG_MX6SLL)
  77         else if ((pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
  78                 clrbits_le32(base + pad_ctrl_ofs, PAD_CTL_IPD_BIT);
  79 #endif
  80 #endif
  81
  82 #ifdef CONFIG_IOMUX_LPSR
  83         if (lpsr == IOMUX_CONFIG_LPSR)
  84                 base = (void *)IOMUXC_BASE_ADDR;
  85 #endif
  86
  87 }
  88
  89 /* configures a list of pads within declared with IOMUX_PADS macro */
  90 void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
  91                                       unsigned count)
  92 {
  93         iomux_v3_cfg_t const *p = pad_list;
  94         int stride;
  95         int i;
  96
  97 #if defined(CONFIG_MX6QDL)
  98         stride = 2;
  99         if (!is_mx6dq() && !is_mx6dqp())
 100                 p += 1;
 101 #else
 102         stride = 1;
 103 #endif
 104         for (i = 0; i < count; i++) {
 105                 imx_iomux_v3_setup_pad(*p);
 106                 p += stride;
 107         }
 108 }
 109
 110 void imx_iomux_set_gpr_register(int group, int start_bit,
 111                                         int num_bits, int value)
 112 {
 113         int i = 0;
 114         u32 reg;
 115         reg = readl(base + group * 4);
 116         while (num_bits) {
 117                 reg &= ~(1<<(start_bit + i));
 118                 i++;
 119                 num_bits--;
 120         }
 121         reg |= (value << start_bit);
 122         writel(reg, base + group * 4);
 123 }
 124
 125 #ifdef CONFIG_IOMUX_SHARE_CONF_REG
 126 void imx_iomux_gpio_set_direction(unsigned int gpio,
 127                                 unsigned int direction)
 128 {
 129         u32 reg;
 130         /*
 131          * Only on Vybrid the input/output buffer enable flags
 132          * are part of the shared mux/conf register.
 133          */
 134         reg = readl(base + (gpio << 2));
 135
 136         if (direction)
 137                 reg |= 0x2;
 138         else
 139                 reg &= ~0x2;
 140
 141         writel(reg, base + (gpio << 2));
 142 }
 143
 144 void imx_iomux_gpio_get_function(unsigned int gpio, u32 *gpio_state)
 145 {
 146         *gpio_state = readl(base + (gpio << 2)) &
 147                 ((0X07 << PAD_MUX_MODE_SHIFT) | PAD_CTL_OBE_IBE_ENABLE);
 148 }
 149 #endif