arch/arm/mach-imx/mx7/psci-mx7.c

   1 /*
   2  * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
   3  * Copyright 2017 NXP
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <asm/io.h>
   9 #include <asm/psci.h>
  10 #include <asm/secure.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <common.h>
  13 #include <fsl_wdog.h>
  14
  15 #define GPC_CPU_PGC_SW_PDN_REQ  0xfc
  16 #define GPC_CPU_PGC_SW_PUP_REQ  0xf0
  17 #define GPC_PGC_C1              0x840
  18
  19 #define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7      0x2
  20
  21 /* below is for i.MX7D */
  22 #define SRC_GPR1_MX7D           0x074
  23 #define SRC_A7RCR0              0x004
  24 #define SRC_A7RCR1              0x008
  25
  26 #define BP_SRC_A7RCR0_A7_CORE_RESET0    0
  27 #define BP_SRC_A7RCR1_A7_CORE1_ENABLE   1
  28
  29 #define CCM_ROOT_WDOG           0xbb80
  30 #define CCM_CCGR_WDOG1          0x49c0
  31
  32 static inline void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset)
  33 {
  34         writel(enable, GPC_IPS_BASE_ADDR + offset);
  35 }
  36
  37 __secure void imx_gpcv2_set_core1_power(bool pdn)
  38 {
  39         u32 reg = pdn ? GPC_CPU_PGC_SW_PUP_REQ : GPC_CPU_PGC_SW_PDN_REQ;
  40         u32 val;
  41
  42         imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C1);
  43
  44         val = readl(GPC_IPS_BASE_ADDR + reg);
  45         val |= BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7;
  46         writel(val, GPC_IPS_BASE_ADDR + reg);
  47
  48         while ((readl(GPC_IPS_BASE_ADDR + reg) &
  49                BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7) != 0)
  50                 ;
  51
  52         imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C1);
  53 }
  54
  55 __secure void imx_enable_cpu_ca7(int cpu, bool enable)
  56 {
  57         u32 mask, val;
  58
  59         mask = 1 << (BP_SRC_A7RCR1_A7_CORE1_ENABLE + cpu - 1);
  60         val = readl(SRC_BASE_ADDR + SRC_A7RCR1);
  61         val = enable ? val | mask : val & ~mask;
  62         writel(val, SRC_BASE_ADDR + SRC_A7RCR1);
  63 }
  64
  65 __secure int imx_cpu_on(int fn, int cpu, int pc)
  66 {
  67         writel(pc, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D);
  68         imx_gpcv2_set_core1_power(true);
  69         imx_enable_cpu_ca7(cpu, true);
  70         return 0;
  71 }
  72
  73 __secure int imx_cpu_off(int cpu)
  74 {
  75         imx_enable_cpu_ca7(cpu, false);
  76         imx_gpcv2_set_core1_power(false);
  77         writel(0, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D + 4);
  78         return 0;
  79 }
  80
  81 __secure void imx_system_reset(void)
  82 {
  83         struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  84
  85         /* make sure WDOG1 clock is enabled */
  86         writel(0x1 << 28, CCM_BASE_ADDR + CCM_ROOT_WDOG);
  87         writel(0x3, CCM_BASE_ADDR + CCM_CCGR_WDOG1);
  88         writew(WCR_WDE, &wdog->wcr);
  89 }