arch/arm/mach-keystone/include/mach/clock.h

   1 /*
   2  * keystone2: common clock header file
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __ASM_ARCH_CLOCK_H
  11 #define __ASM_ARCH_CLOCK_H
  12
  13 #ifndef __ASSEMBLY__
  14
  15 #ifdef CONFIG_SOC_K2HK
  16 #include <asm/arch/clock-k2hk.h>
  17 #endif
  18
  19 #ifdef CONFIG_SOC_K2E
  20 #include <asm/arch/clock-k2e.h>
  21 #endif
  22
  23 #ifdef CONFIG_SOC_K2L
  24 #include <asm/arch/clock-k2l.h>
  25 #endif
  26
  27 #define CORE_PLL MAIN_PLL
  28 #define DDR3_PLL DDR3A_PLL
  29
  30 #define CLK_LIST(CLK)\
  31         CLK(0, core_pll_clk)\
  32         CLK(1, pass_pll_clk)\
  33         CLK(2, tetris_pll_clk)\
  34         CLK(3, ddr3a_pll_clk)\
  35         CLK(4, ddr3b_pll_clk)\
  36         CLK(5, sys_clk0_clk)\
  37         CLK(6, sys_clk0_1_clk)\
  38         CLK(7, sys_clk0_2_clk)\
  39         CLK(8, sys_clk0_3_clk)\
  40         CLK(9, sys_clk0_4_clk)\
  41         CLK(10, sys_clk0_6_clk)\
  42         CLK(11, sys_clk0_8_clk)\
  43         CLK(12, sys_clk0_12_clk)\
  44         CLK(13, sys_clk0_24_clk)\
  45         CLK(14, sys_clk1_clk)\
  46         CLK(15, sys_clk1_3_clk)\
  47         CLK(16, sys_clk1_4_clk)\
  48         CLK(17, sys_clk1_6_clk)\
  49         CLK(18, sys_clk1_12_clk)\
  50         CLK(19, sys_clk2_clk)\
  51         CLK(20, sys_clk3_clk)
  52
  53 #include <asm/types.h>
  54
  55 #define GENERATE_ENUM(NUM, ENUM) ENUM = NUM,
  56 #define GENERATE_INDX_STR(NUM, STRING) #NUM"\t- "#STRING"\n"
  57 #define CLOCK_INDEXES_LIST      CLK_LIST(GENERATE_INDX_STR)
  58
  59 enum {
  60         SPD800,
  61         SPD850,
  62         SPD1000,
  63         SPD1200,
  64         SPD1250,
  65         SPD1350,
  66         SPD1400,
  67         SPD1500,
  68         NUM_SPDS,
  69 };
  70
  71 /* PLL identifiers */
  72 enum {
  73         MAIN_PLL,
  74         TETRIS_PLL,
  75         PASS_PLL,
  76         DDR3A_PLL,
  77         DDR3B_PLL,
  78         MAX_PLL_COUNT,
  79 };
  80
  81 enum ext_clk_e {
  82         sys_clk,
  83         alt_core_clk,
  84         pa_clk,
  85         tetris_clk,
  86         ddr3a_clk,
  87         ddr3b_clk,
  88         ext_clk_count /* number of external clocks */
  89 };
  90
  91 enum clk_e {
  92         CLK_LIST(GENERATE_ENUM)
  93 };
  94
  95 struct keystone_pll_regs {
  96         u32 reg0;
  97         u32 reg1;
  98 };
  99
 100 /* PLL configuration data */
 101 struct pll_init_data {
 102         int pll;
 103         int pll_m;              /* PLL Multiplier */
 104         int pll_d;              /* PLL divider */
 105         int pll_od;             /* PLL output divider */
 106 };
 107
 108 extern unsigned int external_clk[ext_clk_count];
 109 extern const struct keystone_pll_regs keystone_pll_regs[];
 110 extern s16 divn_val[];
 111 extern int speeds[];
 112
 113 void init_plls(void);
 114 void init_pll(const struct pll_init_data *data);
 115 struct pll_init_data *get_pll_init_data(int pll);
 116 unsigned long clk_get_rate(unsigned int clk);
 117 unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
 118 int clk_set_rate(unsigned int clk, unsigned long hz);
 119 int get_max_dev_speed(void);
 120 int get_max_arm_speed(void);
 121 void pll_pa_clk_sel(void);
 122
 123 #endif
 124 #endif