2 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
3 * Copyright (C) 2016 Grinn
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/clock.h>
9 #include <asm/arch/iomux.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/crm_regs.h>
12 #include <asm/arch/mx6ul_pins.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/sys_proto.h>
16 #include <asm/imx-common/iomux-v3.h>
17 #include <asm/imx-common/boot_mode.h>
20 #include <fsl_esdhc.h>
21 #include <linux/sizes.h>
24 DECLARE_GLOBAL_DATA_PTR
;
26 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
27 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
28 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
32 gd
->ram_size
= imx_ddr_size();
37 static iomux_v3_cfg_t
const emmc_pads
[] = {
38 MX6_PAD_NAND_RE_B__USDHC2_CLK
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
39 MX6_PAD_NAND_WE_B__USDHC2_CMD
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
40 MX6_PAD_NAND_DATA00__USDHC2_DATA0
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
41 MX6_PAD_NAND_DATA01__USDHC2_DATA1
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
42 MX6_PAD_NAND_DATA02__USDHC2_DATA2
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
43 MX6_PAD_NAND_DATA03__USDHC2_DATA3
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
44 MX6_PAD_NAND_DATA04__USDHC2_DATA4
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
45 MX6_PAD_NAND_DATA05__USDHC2_DATA5
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
46 MX6_PAD_NAND_DATA06__USDHC2_DATA6
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
47 MX6_PAD_NAND_DATA07__USDHC2_DATA7
| MUX_PAD_CTRL(USDHC_PAD_CTRL
),
50 MX6_PAD_NAND_ALE__GPIO4_IO10
| MUX_PAD_CTRL(NO_PAD_CTRL
),
53 #ifdef CONFIG_FSL_ESDHC
54 static struct fsl_esdhc_cfg emmc_cfg
= {USDHC2_BASE_ADDR
, 0, 8};
56 #define EMMC_PWR_GPIO IMX_GPIO_NR(4, 10)
58 int litesom_mmc_init(bd_t
*bis
)
63 imx_iomux_v3_setup_multiple_pads(emmc_pads
, ARRAY_SIZE(emmc_pads
));
64 gpio_direction_output(EMMC_PWR_GPIO
, 0);
66 gpio_direction_output(EMMC_PWR_GPIO
, 1);
67 emmc_cfg
.sdhc_clk
= mxc_get_clock(MXC_ESDHC2_CLK
);
69 ret
= fsl_esdhc_initialize(bis
, &emmc_cfg
);
71 printf("Warning: failed to initialize mmc dev 1 (eMMC)\n");
79 #ifdef CONFIG_SPL_BUILD
82 #include <asm/arch/mx6-ddr.h>
85 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs
= {
86 .grp_addds
= 0x00000030,
87 .grp_ddrmode_ctl
= 0x00020000,
88 .grp_b0ds
= 0x00000030,
89 .grp_ctlds
= 0x00000030,
90 .grp_b1ds
= 0x00000030,
91 .grp_ddrpke
= 0x00000000,
92 .grp_ddrmode
= 0x00020000,
93 .grp_ddr_type
= 0x000c0000,
96 static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs
= {
97 .dram_dqm0
= 0x00000030,
98 .dram_dqm1
= 0x00000030,
99 .dram_ras
= 0x00000030,
100 .dram_cas
= 0x00000030,
101 .dram_odt0
= 0x00000030,
102 .dram_odt1
= 0x00000030,
103 .dram_sdba2
= 0x00000000,
104 .dram_sdclk_0
= 0x00000030,
105 .dram_sdqs0
= 0x00000030,
106 .dram_sdqs1
= 0x00000030,
107 .dram_reset
= 0x00000030,
110 static struct mx6_mmdc_calibration mx6_mmcd_calib
= {
111 .p0_mpwldectrl0
= 0x00000000,
112 .p0_mpdgctrl0
= 0x41570155,
113 .p0_mprddlctl
= 0x4040474A,
114 .p0_mpwrdlctl
= 0x40405550,
117 struct mx6_ddr_sysinfo ddr_sysinfo
= {
123 .rtt_nom
= 1, /* RTT_Nom = RZQ/2 */
124 .walat
= 0, /* Write additional latency */
125 .ralat
= 5, /* Read additional latency */
126 .mif3_mode
= 3, /* Command prediction working mode */
127 .bi_on
= 1, /* Bank interleaving enabled */
128 .sde_to_rst
= 0x10, /* 14 cycles, 200us (JEDEC default) */
129 .rst_to_cke
= 0x23, /* 33 cycles, 500us (JEDEC default) */
130 .ddr_type
= DDR_TYPE_DDR3
,
131 .refsel
= 0, /* Refresh cycles at 64KHz */
132 .refr
= 1, /* 2 refresh commands per refresh cycle */
135 static struct mx6_ddr3_cfg mem_ddr
= {
148 static void ccgr_init(void)
150 struct mxc_ccm_reg
*ccm
= (struct mxc_ccm_reg
*)CCM_BASE_ADDR
;
152 writel(0xFFFFFFFF, &ccm
->CCGR0
);
153 writel(0xFFFFFFFF, &ccm
->CCGR1
);
154 writel(0xFFFFFFFF, &ccm
->CCGR2
);
155 writel(0xFFFFFFFF, &ccm
->CCGR3
);
156 writel(0xFFFFFFFF, &ccm
->CCGR4
);
157 writel(0xFFFFFFFF, &ccm
->CCGR5
);
158 writel(0xFFFFFFFF, &ccm
->CCGR6
);
159 writel(0xFFFFFFFF, &ccm
->CCGR7
);
162 static void spl_dram_init(void)
164 unsigned long ram_size
;
166 mx6ul_dram_iocfg(mem_ddr
.width
, &mx6_ddr_ioregs
, &mx6_grp_ioregs
);
167 mx6_dram_cfg(&ddr_sysinfo
, &mx6_mmcd_calib
, &mem_ddr
);
170 * Get actual RAM size, so we can adjust DDR row size for <512M
173 ram_size
= get_ram_size((void *)CONFIG_SYS_SDRAM_BASE
, SZ_512M
);
174 if (ram_size
< SZ_512M
) {
175 mem_ddr
.rowaddr
= 14;
176 mx6_dram_cfg(&ddr_sysinfo
, &mx6_mmcd_calib
, &mem_ddr
);
180 void litesom_init_f(void)
184 /* setup AIPS and disable watchdog */
187 #ifdef CONFIG_BOARD_EARLY_INIT_F
188 board_early_init_f();
194 /* UART clocks enabled and gd valid - init serial console */
195 preloader_console_init();
197 /* DDR initialization */