arch/arm/mach-omap2/am33xx/board.c

   1 /*
   2  * board.c
   3  *
   4  * Common board functions for AM33XX based boards
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <dm.h>
  13 #include <debug_uart.h>
  14 #include <errno.h>
  15 #include <ns16550.h>
  16 #include <spl.h>
  17 #include <asm/arch/cpu.h>
  18 #include <asm/arch/hardware.h>
  19 #include <asm/arch/omap.h>
  20 #include <asm/arch/ddr_defs.h>
  21 #include <asm/arch/clock.h>
  22 #include <asm/arch/gpio.h>
  23 #include <asm/arch/mem.h>
  24 #include <asm/arch/mmc_host_def.h>
  25 #include <asm/arch/sys_proto.h>
  26 #include <asm/io.h>
  27 #include <asm/emif.h>
  28 #include <asm/gpio.h>
  29 #include <asm/omap_common.h>
  30 #include <i2c.h>
  31 #include <miiphy.h>
  32 #include <cpsw.h>
  33 #include <linux/errno.h>
  34 #include <linux/compiler.h>
  35 #include <linux/usb/ch9.h>
  36 #include <linux/usb/gadget.h>
  37 #include <linux/usb/musb.h>
  38 #include <asm/omap_musb.h>
  39 #include <asm/davinci_rtc.h>
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 int dram_init(void)
  44 {
  45 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  46         sdram_init();
  47 #endif
  48
  49         /* dram_init must store complete ramsize in gd->ram_size */
  50         gd->ram_size = get_ram_size(
  51                         (void *)CONFIG_SYS_SDRAM_BASE,
  52                         CONFIG_MAX_RAM_BANK_SIZE);
  53         return 0;
  54 }
  55
  56 int dram_init_banksize(void)
  57 {
  58         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  59         gd->bd->bi_dram[0].size = gd->ram_size;
  60
  61         return 0;
  62 }
  63
  64 #if !CONFIG_IS_ENABLED(OF_CONTROL)
  65 static const struct ns16550_platdata am33xx_serial[] = {
  66         { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
  67           .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  68 # ifdef CONFIG_SYS_NS16550_COM2
  69         { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2,
  70           .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  71 #  ifdef CONFIG_SYS_NS16550_COM3
  72         { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2,
  73           .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  74         { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2,
  75           .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  76         { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2,
  77           .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  78         { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2,
  79           .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
  80 #  endif
  81 # endif
  82 };
  83
  84 U_BOOT_DEVICES(am33xx_uarts) = {
  85         { "ns16550_serial", &am33xx_serial[0] },
  86 #  ifdef CONFIG_SYS_NS16550_COM2
  87         { "ns16550_serial", &am33xx_serial[1] },
  88 #   ifdef CONFIG_SYS_NS16550_COM3
  89         { "ns16550_serial", &am33xx_serial[2] },
  90         { "ns16550_serial", &am33xx_serial[3] },
  91         { "ns16550_serial", &am33xx_serial[4] },
  92         { "ns16550_serial", &am33xx_serial[5] },
  93 #   endif
  94 #  endif
  95 };
  96
  97 #ifdef CONFIG_DM_GPIO
  98 static const struct omap_gpio_platdata am33xx_gpio[] = {
  99         { 0, AM33XX_GPIO0_BASE },
 100         { 1, AM33XX_GPIO1_BASE },
 101         { 2, AM33XX_GPIO2_BASE },
 102         { 3, AM33XX_GPIO3_BASE },
 103 #ifdef CONFIG_AM43XX
 104         { 4, AM33XX_GPIO4_BASE },
 105         { 5, AM33XX_GPIO5_BASE },
 106 #endif
 107 };
 108
 109 U_BOOT_DEVICES(am33xx_gpios) = {
 110         { "gpio_omap", &am33xx_gpio[0] },
 111         { "gpio_omap", &am33xx_gpio[1] },
 112         { "gpio_omap", &am33xx_gpio[2] },
 113         { "gpio_omap", &am33xx_gpio[3] },
 114 #ifdef CONFIG_AM43XX
 115         { "gpio_omap", &am33xx_gpio[4] },
 116         { "gpio_omap", &am33xx_gpio[5] },
 117 #endif
 118 };
 119 #endif
 120 #endif
 121
 122 #ifndef CONFIG_DM_GPIO
 123 static const struct gpio_bank gpio_bank_am33xx[] = {
 124         { (void *)AM33XX_GPIO0_BASE },
 125         { (void *)AM33XX_GPIO1_BASE },
 126         { (void *)AM33XX_GPIO2_BASE },
 127         { (void *)AM33XX_GPIO3_BASE },
 128 #ifdef CONFIG_AM43XX
 129         { (void *)AM33XX_GPIO4_BASE },
 130         { (void *)AM33XX_GPIO5_BASE },
 131 #endif
 132 };
 133
 134 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
 135 #endif
 136
 137 #if defined(CONFIG_MMC_OMAP_HS)
 138 int cpu_mmc_init(bd_t *bis)
 139 {
 140         int ret;
 141
 142         ret = omap_mmc_init(0, 0, 0, -1, -1);
 143         if (ret)
 144                 return ret;
 145
 146         return omap_mmc_init(1, 0, 0, -1, -1);
 147 }
 148 #endif
 149
 150 /* AM33XX has two MUSB controllers which can be host or gadget */
 151 #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
 152         (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
 153         (!defined(CONFIG_DM_USB))
 154 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 155
 156 /* USB 2.0 PHY Control */
 157 #define CM_PHY_PWRDN                    (1 << 0)
 158 #define CM_PHY_OTG_PWRDN                (1 << 1)
 159 #define OTGVDET_EN                      (1 << 19)
 160 #define OTGSESSENDEN                    (1 << 20)
 161
 162 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
 163 {
 164         if (on) {
 165                 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
 166                                 OTGVDET_EN | OTGSESSENDEN);
 167         } else {
 168                 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
 169         }
 170 }
 171
 172 static struct musb_hdrc_config musb_config = {
 173         .multipoint     = 1,
 174         .dyn_fifo       = 1,
 175         .num_eps        = 16,
 176         .ram_bits       = 12,
 177 };
 178
 179 #ifdef CONFIG_AM335X_USB0
 180 static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on)
 181 {
 182         am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
 183 }
 184
 185 struct omap_musb_board_data otg0_board_data = {
 186         .set_phy_power = am33xx_otg0_set_phy_power,
 187 };
 188
 189 static struct musb_hdrc_platform_data otg0_plat = {
 190         .mode           = CONFIG_AM335X_USB0_MODE,
 191         .config         = &musb_config,
 192         .power          = 50,
 193         .platform_ops   = &musb_dsps_ops,
 194         .board_data     = &otg0_board_data,
 195 };
 196 #endif
 197
 198 #ifdef CONFIG_AM335X_USB1
 199 static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on)
 200 {
 201         am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
 202 }
 203
 204 struct omap_musb_board_data otg1_board_data = {
 205         .set_phy_power = am33xx_otg1_set_phy_power,
 206 };
 207
 208 static struct musb_hdrc_platform_data otg1_plat = {
 209         .mode           = CONFIG_AM335X_USB1_MODE,
 210         .config         = &musb_config,
 211         .power          = 50,
 212         .platform_ops   = &musb_dsps_ops,
 213         .board_data     = &otg1_board_data,
 214 };
 215 #endif
 216 #endif
 217
 218 int arch_misc_init(void)
 219 {
 220 #ifndef CONFIG_DM_USB
 221 #ifdef CONFIG_AM335X_USB0
 222         musb_register(&otg0_plat, &otg0_board_data,
 223                 (void *)USB0_OTG_BASE);
 224 #endif
 225 #ifdef CONFIG_AM335X_USB1
 226         musb_register(&otg1_plat, &otg1_board_data,
 227                 (void *)USB1_OTG_BASE);
 228 #endif
 229 #else
 230         struct udevice *dev;
 231         int ret;
 232
 233         ret = uclass_first_device(UCLASS_MISC, &dev);
 234         if (ret || !dev)
 235                 return ret;
 236
 237 #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
 238         ret = usb_ether_init();
 239         if (ret) {
 240                 error("USB ether init failed\n");
 241                 return ret;
 242         }
 243 #endif
 244 #endif
 245         return 0;
 246 }
 247
 248 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 249 /*
 250  * In the case of non-SPL based booting we'll want to call these
 251  * functions a tiny bit later as it will require gd to be set and cleared
 252  * and that's not true in s_init in this case so we cannot do it there.
 253  */
 254 int board_early_init_f(void)
 255 {
 256         prcm_init();
 257         set_mux_conf_regs();
 258
 259         return 0;
 260 }
 261
 262 /*
 263  * This function is the place to do per-board things such as ramp up the
 264  * MPU clock frequency.
 265  */
 266 __weak void am33xx_spl_board_init(void)
 267 {
 268 }
 269
 270 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
 271 static void rtc32k_enable(void)
 272 {
 273         struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
 274
 275         /*
 276          * Unlock the RTC's registers.  For more details please see the
 277          * RTC_SS section of the TRM.  In order to unlock we need to
 278          * write these specific values (keys) in this order.
 279          */
 280         writel(RTC_KICK0R_WE, &rtc->kick0r);
 281         writel(RTC_KICK1R_WE, &rtc->kick1r);
 282
 283         /* Enable the RTC 32K OSC by setting bits 3 and 6. */
 284         writel((1 << 3) | (1 << 6), &rtc->osc);
 285 }
 286 #endif
 287
 288 static void uart_soft_reset(void)
 289 {
 290         struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
 291         u32 regval;
 292
 293         regval = readl(&uart_base->uartsyscfg);
 294         regval |= UART_RESET;
 295         writel(regval, &uart_base->uartsyscfg);
 296         while ((readl(&uart_base->uartsyssts) &
 297                 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
 298                 ;
 299
 300         /* Disable smart idle */
 301         regval = readl(&uart_base->uartsyscfg);
 302         regval |= UART_SMART_IDLE_EN;
 303         writel(regval, &uart_base->uartsyscfg);
 304 }
 305
 306 static void watchdog_disable(void)
 307 {
 308         struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
 309
 310         writel(0xAAAA, &wdtimer->wdtwspr);
 311         while (readl(&wdtimer->wdtwwps) != 0x0)
 312                 ;
 313         writel(0x5555, &wdtimer->wdtwspr);
 314         while (readl(&wdtimer->wdtwwps) != 0x0)
 315                 ;
 316 }
 317
 318 void s_init(void)
 319 {
 320 }
 321
 322 void early_system_init(void)
 323 {
 324         /*
 325          * The ROM will only have set up sufficient pinmux to allow for the
 326          * first 4KiB NOR to be read, we must finish doing what we know of
 327          * the NOR mux in this space in order to continue.
 328          */
 329 #ifdef CONFIG_NOR_BOOT
 330         enable_norboot_pin_mux();
 331 #endif
 332         watchdog_disable();
 333         set_uart_mux_conf();
 334         setup_early_clocks();
 335         uart_soft_reset();
 336 #ifdef CONFIG_SPL_BUILD
 337         /*
 338          * Save the boot parameters passed from romcode.
 339          * We cannot delay the saving further than this,
 340          * to prevent overwrites.
 341          */
 342         save_omap_boot_params();
 343 #endif
 344 #ifdef CONFIG_DEBUG_UART_OMAP
 345         debug_uart_init();
 346 #endif
 347 #ifdef CONFIG_TI_I2C_BOARD_DETECT
 348         do_board_detect();
 349 #endif
 350 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
 351         /* Enable RTC32K clock */
 352         rtc32k_enable();
 353 #endif
 354 }
 355
 356 #ifdef CONFIG_SPL_BUILD
 357 void board_init_f(ulong dummy)
 358 {
 359         hw_data_init();
 360         early_system_init();
 361         board_early_init_f();
 362         sdram_init();
 363         /* dram_init must store complete ramsize in gd->ram_size */
 364         gd->ram_size = get_ram_size(
 365                         (void *)CONFIG_SYS_SDRAM_BASE,
 366                         CONFIG_MAX_RAM_BANK_SIZE);
 367 }
 368 #endif
 369
 370 #endif
 371
 372 int arch_cpu_init_dm(void)
 373 {
 374         hw_data_init();
 375 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 376         early_system_init();
 377 #endif
 378         return 0;
 379 }