arch/arm/mach-omap2/omap3/spl_id_nand.c

   1 /*
   2  * (C) Copyright 2011
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * Author :
   6  *     Tom Rini <trini@ti.com>
   7  *
   8  * Initial Code from:
   9  *     Richard Woodruff <r-woodruff2@ti.com>
  10  *     Jian Zhang <jzhang@ti.com>
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14
  15 #include <common.h>
  16 #include <jffs2/load_kernel.h>
  17 #include <linux/mtd/rawnand.h>
  18 #include <linux/mtd/omap_gpmc.h>
  19 #include <asm/io.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/arch/mem.h>
  22
  23 /*
  24  * Many boards will want to know the results of the NAND_CMD_READID command
  25  * in order to decide what to do about DDR initialization.  This function
  26  * allows us to do that very early and to pass those results back to the
  27  * board so it can make whatever decisions need to be made.
  28  */
  29 int identify_nand_chip(int *mfr, int *id)
  30 {
  31         int loops = 1000;
  32
  33         /* Make sure that we have setup GPMC for NAND correctly. */
  34         set_gpmc_cs0(MTD_DEV_TYPE_NAND);
  35
  36         sdelay(2000);
  37
  38         /* Issue a RESET and then READID */
  39         writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
  40         writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
  41         while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
  42                                                 != NAND_STATUS_READY) {
  43                 sdelay(100);
  44                 if (--loops == 0)
  45                         return 1;
  46         }
  47         writeb(NAND_CMD_READID, &gpmc_cfg->cs[0].nand_cmd);
  48
  49         /* Set the address to read to 0x0 */
  50         writeb(0x0, &gpmc_cfg->cs[0].nand_adr);
  51
  52         /* Read off the manufacturer and device id. */
  53         *mfr = readb(&gpmc_cfg->cs[0].nand_dat);
  54         *id = readb(&gpmc_cfg->cs[0].nand_dat);
  55
  56         return 0;
  57 }