2 * Timing and Organization details of the ddr device parts used in OMAP5
6 * Texas Instruments, <www.ti.com>
8 * Aneesh V <aneesh@ti.com>
9 * Sricharan R <r.sricharan@ti.com>
11 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/sys_proto.h>
18 * This file provides details of the LPDDR2 SDRAM parts used on OMAP5
19 * EVM. Since the parts used and geometry are identical for
20 * evm for a given OMAP5 revision, this information is kept
21 * here instead of being in board directory. However the key functions
22 * exported are weakly linked so that they can be over-ridden in the board
23 * directory if there is a OMAP5 board in the future that uses a different
24 * memory device or geometry.
26 * For any new board with different memory devices over-ride one or more
27 * of the following functions as per the CONFIG flags you intend to enable:
28 * - emif_get_reg_dump()
29 * - emif_get_dmm_regs()
30 * - emif_get_device_details()
31 * - emif_get_device_timings()
34 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
35 const struct emif_regs emif_regs_532_mhz_2cs
= {
36 .sdram_config_init
= 0x80800EBA,
37 .sdram_config
= 0x808022BA,
38 .ref_ctrl
= 0x0000081A,
39 .sdram_tim1
= 0x772F6873,
40 .sdram_tim2
= 0x304a129a,
41 .sdram_tim3
= 0x02f7e45f,
42 .read_idle_ctrl
= 0x00050000,
43 .zq_config
= 0x000b3215,
44 .temp_alert_config
= 0x08000a05,
45 .emif_ddr_phy_ctlr_1_init
= 0x0E28420d,
46 .emif_ddr_phy_ctlr_1
= 0x0E28420d,
47 .emif_ddr_ext_phy_ctrl_1
= 0x04020080,
48 .emif_ddr_ext_phy_ctrl_2
= 0x28C518A3,
49 .emif_ddr_ext_phy_ctrl_3
= 0x518A3146,
50 .emif_ddr_ext_phy_ctrl_4
= 0x0014628C,
51 .emif_ddr_ext_phy_ctrl_5
= 0x04010040
54 const struct emif_regs emif_regs_532_mhz_2cs_es2
= {
55 .sdram_config_init
= 0x80800EBA,
56 .sdram_config
= 0x808022BA,
57 .ref_ctrl
= 0x0000081A,
58 .sdram_tim1
= 0x772F6873,
59 .sdram_tim2
= 0x304a129a,
60 .sdram_tim3
= 0x02f7e45f,
61 .read_idle_ctrl
= 0x00050000,
62 .zq_config
= 0x100b3215,
63 .temp_alert_config
= 0x08000a05,
64 .emif_ddr_phy_ctlr_1_init
= 0x0E30400d,
65 .emif_ddr_phy_ctlr_1
= 0x0E30400d,
66 .emif_ddr_ext_phy_ctrl_1
= 0x04020080,
67 .emif_ddr_ext_phy_ctrl_2
= 0x28C518A3,
68 .emif_ddr_ext_phy_ctrl_3
= 0x518A3146,
69 .emif_ddr_ext_phy_ctrl_4
= 0x0014628C,
70 .emif_ddr_ext_phy_ctrl_5
= 0xC330CC33,
73 const struct emif_regs emif_regs_266_mhz_2cs
= {
74 .sdram_config_init
= 0x80800EBA,
75 .sdram_config
= 0x808022BA,
76 .ref_ctrl
= 0x0000040D,
77 .sdram_tim1
= 0x2A86B419,
78 .sdram_tim2
= 0x1025094A,
79 .sdram_tim3
= 0x026BA22F,
80 .read_idle_ctrl
= 0x00050000,
81 .zq_config
= 0x000b3215,
82 .temp_alert_config
= 0x08000a05,
83 .emif_ddr_phy_ctlr_1_init
= 0x0E28420d,
84 .emif_ddr_phy_ctlr_1
= 0x0E28420d,
85 .emif_ddr_ext_phy_ctrl_1
= 0x04020080,
86 .emif_ddr_ext_phy_ctrl_2
= 0x0A414829,
87 .emif_ddr_ext_phy_ctrl_3
= 0x14829052,
88 .emif_ddr_ext_phy_ctrl_4
= 0x000520A4,
89 .emif_ddr_ext_phy_ctrl_5
= 0x04010040
92 const struct emif_regs emif_regs_ddr3_532_mhz_1cs
= {
93 .sdram_config_init
= 0x61851B32,
94 .sdram_config
= 0x61851B32,
96 .ref_ctrl
= 0x00001035,
97 .sdram_tim1
= 0xCCCF36B3,
98 .sdram_tim2
= 0x308F7FDA,
99 .sdram_tim3
= 0x027F88A8,
100 .read_idle_ctrl
= 0x00050000,
101 .zq_config
= 0x0007190B,
102 .temp_alert_config
= 0x00000000,
103 .emif_ddr_phy_ctlr_1_init
= 0x0020420A,
104 .emif_ddr_phy_ctlr_1
= 0x0024420A,
105 .emif_ddr_ext_phy_ctrl_1
= 0x04040100,
106 .emif_ddr_ext_phy_ctrl_2
= 0x00000000,
107 .emif_ddr_ext_phy_ctrl_3
= 0x00000000,
108 .emif_ddr_ext_phy_ctrl_4
= 0x00000000,
109 .emif_ddr_ext_phy_ctrl_5
= 0x04010040,
110 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
111 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
112 .emif_rd_wr_lvl_ctl
= 0x00000000,
113 .emif_rd_wr_exec_thresh
= 0x00000305
116 const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2
= {
117 .sdram_config_init
= 0x61851B32,
118 .sdram_config
= 0x61851B32,
119 .sdram_config2
= 0x0,
120 .ref_ctrl
= 0x00001035,
121 .sdram_tim1
= 0xCCCF36B3,
122 .sdram_tim2
= 0x308F7FDA,
123 .sdram_tim3
= 0x027F88A8,
124 .read_idle_ctrl
= 0x00050000,
125 .zq_config
= 0x1007190B,
126 .temp_alert_config
= 0x00000000,
127 .emif_ddr_phy_ctlr_1_init
= 0x0030400A,
128 .emif_ddr_phy_ctlr_1
= 0x0034400A,
129 .emif_ddr_ext_phy_ctrl_1
= 0x04040100,
130 .emif_ddr_ext_phy_ctrl_2
= 0x00000000,
131 .emif_ddr_ext_phy_ctrl_3
= 0x00000000,
132 .emif_ddr_ext_phy_ctrl_4
= 0x00000000,
133 .emif_ddr_ext_phy_ctrl_5
= 0x4350D435,
134 .emif_rd_wr_lvl_rmp_win
= 0x00000000,
135 .emif_rd_wr_lvl_rmp_ctl
= 0x80000000,
136 .emif_rd_wr_lvl_ctl
= 0x00000000,
137 .emif_rd_wr_exec_thresh
= 0x40000305
140 const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2
= {
141 .dmm_lisa_map_0
= 0x0,
142 .dmm_lisa_map_1
= 0x0,
143 .dmm_lisa_map_2
= 0x80740300,
144 .dmm_lisa_map_3
= 0xFF020100,
148 static void emif_get_reg_dump_sdp(u32 emif_nr
, const struct emif_regs
**regs
)
150 switch (omap_revision()) {
152 *regs
= &emif_regs_532_mhz_2cs
;
155 *regs
= &emif_regs_ddr3_532_mhz_1cs
;
158 *regs
= &emif_regs_532_mhz_2cs_es2
;
162 *regs
= &emif_regs_ddr3_532_mhz_1cs_es2
;
167 void emif_get_reg_dump(u32 emif_nr
, const struct emif_regs
**regs
)
168 __attribute__((weak
, alias("emif_get_reg_dump_sdp")));
170 static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
173 switch (omap_revision()) {
179 *dmm_lisa_regs
= &lisa_map_4G_x_2_x_2
;
185 void emif_get_dmm_regs(const struct dmm_lisa_map_regs
**dmm_lisa_regs
)
186 __attribute__((weak
, alias("emif_get_dmm_regs_sdp")));
189 static const struct lpddr2_device_details dev_4G_S4_details
= {
190 .type
= LPDDR2_TYPE_S4
,
191 .density
= LPDDR2_DENSITY_4Gb
,
192 .io_width
= LPDDR2_IO_WIDTH_32
,
193 .manufacturer
= LPDDR2_MANUFACTURER_SAMSUNG
196 static void emif_get_device_details_sdp(u32 emif_nr
,
197 struct lpddr2_device_details
*cs0_device_details
,
198 struct lpddr2_device_details
*cs1_device_details
)
200 /* EMIF1 & EMIF2 have identical configuration */
201 *cs0_device_details
= dev_4G_S4_details
;
202 *cs1_device_details
= dev_4G_S4_details
;
205 void emif_get_device_details(u32 emif_nr
,
206 struct lpddr2_device_details
*cs0_device_details
,
207 struct lpddr2_device_details
*cs1_device_details
)
208 __attribute__((weak
, alias("emif_get_device_details_sdp")));
210 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
212 const u32 ext_phy_ctrl_const_base
[] = {
235 const u32 ddr3_ext_phy_ctrl_const_base_es1
[] = {
258 const u32 ddr3_ext_phy_ctrl_const_base_es2
[] = {
281 /* Ext phy ctrl 1-35 regs */
283 dra_ddr3_ext_phy_ctrl_const_base_es1_emif1
[] = {
321 /* Ext phy ctrl 1-35 regs */
323 dra_ddr3_ext_phy_ctrl_const_base_es1_emif2
[] = {
361 /* Ext phy ctrl 1-35 regs */
363 dra_ddr3_ext_phy_ctrl_const_base_666MHz
[] = {
401 const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2
[] = {
440 const struct lpddr2_mr_regs mr_regs
= {
441 .mr1
= MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8
,
444 .mr10
= MR10_ZQ_ZQINIT
,
445 .mr16
= MR16_REF_FULL_ARRAY
448 void __weak
emif_get_ext_phy_ctrl_const_regs(u32 emif_nr
,
452 switch (omap_revision()) {
455 *regs
= ext_phy_ctrl_const_base
;
456 *size
= ARRAY_SIZE(ext_phy_ctrl_const_base
);
459 *regs
= ddr3_ext_phy_ctrl_const_base_es1
;
460 *size
= ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1
);
463 *regs
= ddr3_ext_phy_ctrl_const_base_es2
;
464 *size
= ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2
);
470 *regs
= dra_ddr3_ext_phy_ctrl_const_base_es1_emif1
;
472 ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1
);
474 *regs
= dra_ddr3_ext_phy_ctrl_const_base_es1_emif2
;
476 ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2
);
480 *regs
= dra_ddr3_ext_phy_ctrl_const_base_666MHz
;
481 *size
= ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz
);
486 *regs
= dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2
;
487 *size
= ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2
);
490 *regs
= ddr3_ext_phy_ctrl_const_base_es2
;
491 *size
= ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2
);
496 void get_lpddr2_mr_regs(const struct lpddr2_mr_regs
**regs
)
501 static void do_ext_phy_settings_omap5(u32 base
, const struct emif_regs
*regs
)
503 u32
*ext_phy_ctrl_base
= 0;
504 u32
*emif_ext_phy_ctrl_base
= 0;
506 const u32
*ext_phy_ctrl_const_regs
;
510 emif_nr
= (base
== EMIF1_BASE
) ? 1 : 2;
512 struct emif_reg_struct
*emif
= (struct emif_reg_struct
*)base
;
514 ext_phy_ctrl_base
= (u32
*) &(regs
->emif_ddr_ext_phy_ctrl_1
);
515 emif_ext_phy_ctrl_base
= (u32
*) &(emif
->emif_ddr_ext_phy_ctrl_1
);
517 /* Configure external phy control timing registers */
518 for (i
= 0; i
< EMIF_EXT_PHY_CTRL_TIMING_REG
; i
++) {
519 writel(*ext_phy_ctrl_base
, emif_ext_phy_ctrl_base
++);
520 /* Update shadow registers */
521 writel(*ext_phy_ctrl_base
++, emif_ext_phy_ctrl_base
++);
525 * external phy 6-24 registers do not change with
528 emif_get_ext_phy_ctrl_const_regs(emif_nr
,
529 &ext_phy_ctrl_const_regs
, &size
);
531 for (i
= 0; i
< size
; i
++) {
532 writel(ext_phy_ctrl_const_regs
[i
],
533 emif_ext_phy_ctrl_base
++);
534 /* Update shadow registers */
535 writel(ext_phy_ctrl_const_regs
[i
],
536 emif_ext_phy_ctrl_base
++);
540 static void do_ext_phy_settings_dra7(u32 base
, const struct emif_regs
*regs
)
542 struct emif_reg_struct
*emif
= (struct emif_reg_struct
*)base
;
543 u32
*emif_ext_phy_ctrl_base
= 0;
545 const u32
*ext_phy_ctrl_const_regs
;
546 u32 i
, hw_leveling
, size
, phy
;
548 emif_nr
= (base
== EMIF1_BASE
) ? 1 : 2;
550 hw_leveling
= regs
->emif_rd_wr_lvl_rmp_ctl
>> EMIF_REG_RDWRLVL_EN_SHIFT
;
551 phy
= regs
->emif_ddr_phy_ctlr_1_init
;
553 emif_ext_phy_ctrl_base
= (u32
*)&(emif
->emif_ddr_ext_phy_ctrl_1
);
555 emif_get_ext_phy_ctrl_const_regs(emif_nr
,
556 &ext_phy_ctrl_const_regs
, &size
);
558 writel(ext_phy_ctrl_const_regs
[0], &emif_ext_phy_ctrl_base
[0]);
559 writel(ext_phy_ctrl_const_regs
[0], &emif_ext_phy_ctrl_base
[1]);
562 * Copy the predefined PHY register values
563 * if leveling is disabled.
565 if (phy
& EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK
)
566 for (i
= 1; i
< 6; i
++) {
567 writel(ext_phy_ctrl_const_regs
[i
],
568 &emif_ext_phy_ctrl_base
[i
* 2]);
569 writel(ext_phy_ctrl_const_regs
[i
],
570 &emif_ext_phy_ctrl_base
[i
* 2 + 1]);
573 if (phy
& EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK
)
574 for (i
= 6; i
< 11; i
++) {
575 writel(ext_phy_ctrl_const_regs
[i
],
576 &emif_ext_phy_ctrl_base
[i
* 2]);
577 writel(ext_phy_ctrl_const_regs
[i
],
578 &emif_ext_phy_ctrl_base
[i
* 2 + 1]);
581 if (phy
& EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK
)
582 for (i
= 11; i
< 25; i
++) {
583 writel(ext_phy_ctrl_const_regs
[i
],
584 &emif_ext_phy_ctrl_base
[i
* 2]);
585 writel(ext_phy_ctrl_const_regs
[i
],
586 &emif_ext_phy_ctrl_base
[i
* 2 + 1]);
591 * Write the init value for HW levling to occur
593 for (i
= 21; i
< 35; i
++) {
594 writel(ext_phy_ctrl_const_regs
[i
],
595 &emif_ext_phy_ctrl_base
[i
* 2]);
596 writel(ext_phy_ctrl_const_regs
[i
],
597 &emif_ext_phy_ctrl_base
[i
* 2 + 1]);
602 void do_ext_phy_settings(u32 base
, const struct emif_regs
*regs
)
605 do_ext_phy_settings_omap5(base
, regs
);
607 do_ext_phy_settings_dra7(base
, regs
);
610 #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
611 static const struct lpddr2_ac_timings timings_jedec_532_mhz
= {
612 .max_freq
= 532000000,
634 static const struct lpddr2_min_tck min_tck
= {
649 static const struct lpddr2_ac_timings
*ac_timings
[MAX_NUM_SPEEDBINS
] = {
650 &timings_jedec_532_mhz
653 static const struct lpddr2_device_timings dev_4G_S4_timings
= {
654 .ac_timings
= ac_timings
,
659 * List of status registers to be controlled back to control registers
660 * after initial leveling
663 const struct read_write_regs omap5_bug_00339_regs
[] = {
678 const struct read_write_regs dra_bug_00339_regs
[] = {
701 const struct read_write_regs
*get_bug_regs(u32
*iterations
)
703 const struct read_write_regs
*bug_00339_regs_ptr
= NULL
;
705 switch (omap_revision()) {
710 bug_00339_regs_ptr
= omap5_bug_00339_regs
;
711 *iterations
= sizeof(omap5_bug_00339_regs
)/
712 sizeof(omap5_bug_00339_regs
[0]);
721 bug_00339_regs_ptr
= dra_bug_00339_regs
;
722 *iterations
= sizeof(dra_bug_00339_regs
)/
723 sizeof(dra_bug_00339_regs
[0]);
726 printf("\n Error: UnKnown SOC");
729 return bug_00339_regs_ptr
;
732 void emif_get_device_timings_sdp(u32 emif_nr
,
733 const struct lpddr2_device_timings
**cs0_device_timings
,
734 const struct lpddr2_device_timings
**cs1_device_timings
)
736 /* Identical devices on EMIF1 & EMIF2 */
737 *cs0_device_timings
= &dev_4G_S4_timings
;
738 *cs1_device_timings
= &dev_4G_S4_timings
;
741 void emif_get_device_timings(u32 emif_nr
,
742 const struct lpddr2_device_timings
**cs0_device_timings
,
743 const struct lpddr2_device_timings
**cs1_device_timings
)
744 __attribute__((weak
, alias("emif_get_device_timings_sdp")));
746 #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */