arch/arm/mach-rockchip/rk3128-board.c

   1 /*
   2  * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <dm.h>
   9 #include <ram.h>
  10 #include <syscon.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/periph.h>
  14 #include <asm/arch/grf_rk3128.h>
  15 #include <asm/arch/boot_mode.h>
  16 #include <asm/arch/timer.h>
  17 #include <power/regulator.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 __weak int rk_board_late_init(void)
  22 {
  23         return 0;
  24 }
  25
  26 int board_late_init(void)
  27 {
  28         setup_boot_mode();
  29
  30         return rk_board_late_init();
  31 }
  32
  33 int board_init(void)
  34 {
  35         int ret = 0;
  36
  37         rockchip_timer_init();
  38
  39         ret = regulators_enable_boot_on(false);
  40         if (ret) {
  41                 debug("%s: Cannot enable boot on regulator\n", __func__);
  42                 return ret;
  43         }
  44
  45         return 0;
  46 }
  47
  48 int dram_init_banksize(void)
  49 {
  50         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  51         gd->bd->bi_dram[0].size = 0x8400000;
  52         /* Reserve 0xe00000(14MB) for OPTEE with TA enabled, otherwise 2MB */
  53         gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
  54                                 + gd->bd->bi_dram[0].size + 0xe00000;
  55         gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
  56                                 + gd->ram_size - gd->bd->bi_dram[1].start;
  57
  58         return 0;
  59 }
  60
  61 #ifndef CONFIG_SYS_DCACHE_OFF
  62 void enable_caches(void)
  63 {
  64         /* Enable D-cache. I-cache is already enabled in start.S */
  65         dcache_enable();
  66 }
  67 #endif
  68
  69 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
  70 #include <usb.h>
  71 #include <usb/dwc2_udc.h>
  72
  73 static struct dwc2_plat_otg_data rk3128_otg_data = {
  74         .rx_fifo_sz     = 512,
  75         .np_tx_fifo_sz  = 16,
  76         .tx_fifo_sz     = 128,
  77 };
  78
  79 int board_usb_init(int index, enum usb_init_type init)
  80 {
  81         int node;
  82         const char *mode;
  83         bool matched = false;
  84         const void *blob = gd->fdt_blob;
  85
  86         /* find the usb_otg node */
  87         node = fdt_node_offset_by_compatible(blob, -1,
  88                                              "rockchip,rk3128-usb");
  89
  90         while (node > 0) {
  91                 mode = fdt_getprop(blob, node, "dr_mode", NULL);
  92                 if (mode && strcmp(mode, "otg") == 0) {
  93                         matched = true;
  94                         break;
  95                 }
  96
  97                 node = fdt_node_offset_by_compatible(blob, node,
  98                                                      "rockchip,rk3128-usb");
  99         }
 100         if (!matched) {
 101                 debug("Not found usb_otg device\n");
 102                 return -ENODEV;
 103         }
 104         rk3128_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
 105
 106         return dwc2_udc_probe(&rk3128_otg_data);
 107 }
 108
 109 int board_usb_cleanup(int index, enum usb_init_type init)
 110 {
 111         return 0;
 112 }
 113 #endif
 114
 115 #if defined(CONFIG_USB_FUNCTION_FASTBOOT)
 116 int fb_set_reboot_flag(void)
 117 {
 118         struct rk3128_grf *grf;
 119
 120         printf("Setting reboot to fastboot flag ...\n");
 121         grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 122         /* Set boot mode to fastboot */
 123         writel(BOOT_FASTBOOT, &grf->os_reg[0]);
 124
 125         return 0;
 126 }
 127 #endif