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[people/ms/u-boot.git] / arch / arm / mach-rockchip / rk3288 / sdram_rk3288.c
1 /*
2 * (C) Copyright 2015 Google, Inc
3 * Copyright 2014 Rockchip Inc.
4 *
5 * SPDX-License-Identifier: GPL-2.0
6 *
7 * Adapted from coreboot.
8 */
9
10 #include <common.h>
11 #include <clk.h>
12 #include <dm.h>
13 #include <dt-structs.h>
14 #include <errno.h>
15 #include <ram.h>
16 #include <regmap.h>
17 #include <syscon.h>
18 #include <asm/io.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/cru_rk3288.h>
21 #include <asm/arch/ddr_rk3288.h>
22 #include <asm/arch/grf_rk3288.h>
23 #include <asm/arch/pmu_rk3288.h>
24 #include <asm/arch/sdram.h>
25 #include <linux/err.h>
26 #include <power/regulator.h>
27 #include <power/rk808_pmic.h>
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 struct chan_info {
32 struct rk3288_ddr_pctl *pctl;
33 struct rk3288_ddr_publ *publ;
34 struct rk3288_msch *msch;
35 };
36
37 struct dram_info {
38 struct chan_info chan[2];
39 struct ram_info info;
40 struct clk ddr_clk;
41 struct rk3288_cru *cru;
42 struct rk3288_grf *grf;
43 struct rk3288_sgrf *sgrf;
44 struct rk3288_pmu *pmu;
45 bool is_veyron;
46 };
47
48 struct rk3288_sdram_params {
49 #if CONFIG_IS_ENABLED(OF_PLATDATA)
50 struct dtd_rockchip_rk3288_dmc of_plat;
51 #endif
52 struct rk3288_sdram_channel ch[2];
53 struct rk3288_sdram_pctl_timing pctl_timing;
54 struct rk3288_sdram_phy_timing phy_timing;
55 struct rk3288_base_params base;
56 int num_channels;
57 struct regmap *map;
58 };
59
60 #ifdef CONFIG_SPL_BUILD
61 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
62 {
63 int i;
64
65 for (i = 0; i < n / sizeof(u32); i++) {
66 writel(*src, dest);
67 src++;
68 dest++;
69 }
70 }
71
72 static void ddr_reset(struct rk3288_cru *cru, u32 ch, u32 ctl, u32 phy)
73 {
74 u32 phy_ctl_srstn_shift = 4 + 5 * ch;
75 u32 ctl_psrstn_shift = 3 + 5 * ch;
76 u32 ctl_srstn_shift = 2 + 5 * ch;
77 u32 phy_psrstn_shift = 1 + 5 * ch;
78 u32 phy_srstn_shift = 5 * ch;
79
80 rk_clrsetreg(&cru->cru_softrst_con[10],
81 1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift |
82 1 << ctl_srstn_shift | 1 << phy_psrstn_shift |
83 1 << phy_srstn_shift,
84 phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift |
85 ctl << ctl_srstn_shift | phy << phy_psrstn_shift |
86 phy << phy_srstn_shift);
87 }
88
89 static void ddr_phy_ctl_reset(struct rk3288_cru *cru, u32 ch, u32 n)
90 {
91 u32 phy_ctl_srstn_shift = 4 + 5 * ch;
92
93 rk_clrsetreg(&cru->cru_softrst_con[10],
94 1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift);
95 }
96
97 static void phy_pctrl_reset(struct rk3288_cru *cru,
98 struct rk3288_ddr_publ *publ,
99 u32 channel)
100 {
101 int i;
102
103 ddr_reset(cru, channel, 1, 1);
104 udelay(1);
105 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
106 for (i = 0; i < 4; i++)
107 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
108
109 udelay(10);
110 setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
111 for (i = 0; i < 4; i++)
112 setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
113
114 udelay(10);
115 ddr_reset(cru, channel, 1, 0);
116 udelay(10);
117 ddr_reset(cru, channel, 0, 0);
118 udelay(10);
119 }
120
121 static void phy_dll_bypass_set(struct rk3288_ddr_publ *publ,
122 u32 freq)
123 {
124 int i;
125 if (freq <= 250000000) {
126 if (freq <= 150000000)
127 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
128 else
129 setbits_le32(&publ->dllgcr, SBIAS_BYPASS);
130 setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
131 for (i = 0; i < 4; i++)
132 setbits_le32(&publ->datx8[i].dxdllcr,
133 DXDLLCR_DLLDIS);
134
135 setbits_le32(&publ->pir, PIR_DLLBYP);
136 } else {
137 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
138 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
139 for (i = 0; i < 4; i++) {
140 clrbits_le32(&publ->datx8[i].dxdllcr,
141 DXDLLCR_DLLDIS);
142 }
143
144 clrbits_le32(&publ->pir, PIR_DLLBYP);
145 }
146 }
147
148 static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype)
149 {
150 writel(DFI_INIT_START, &pctl->dfistcfg0);
151 writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
152 &pctl->dfistcfg1);
153 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
154 writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
155 &pctl->dfilpcfg0);
156
157 writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay);
158 writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata);
159 writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat);
160 writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis);
161 writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken);
162 writel(1, &pctl->dfitphyupdtype0);
163
164 /* cs0 and cs1 write odt enable */
165 writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL),
166 &pctl->dfiodtcfg);
167 /* odt write length */
168 writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
169 /* phyupd and ctrlupd disabled */
170 writel(0, &pctl->dfiupdcfg);
171 }
172
173 static void ddr_set_enable(struct rk3288_grf *grf, uint channel, bool enable)
174 {
175 uint val = 0;
176
177 if (enable) {
178 val = 1 << (channel ? DDR1_16BIT_EN_SHIFT :
179 DDR0_16BIT_EN_SHIFT);
180 }
181 rk_clrsetreg(&grf->soc_con0,
182 1 << (channel ? DDR1_16BIT_EN_SHIFT : DDR0_16BIT_EN_SHIFT),
183 val);
184 }
185
186 static void ddr_set_ddr3_mode(struct rk3288_grf *grf, uint channel,
187 bool ddr3_mode)
188 {
189 uint mask, val;
190
191 mask = 1 << (channel ? MSCH1_MAINDDR3_SHIFT : MSCH0_MAINDDR3_SHIFT);
192 val = ddr3_mode << (channel ? MSCH1_MAINDDR3_SHIFT :
193 MSCH0_MAINDDR3_SHIFT);
194 rk_clrsetreg(&grf->soc_con0, mask, val);
195 }
196
197 static void ddr_set_en_bst_odt(struct rk3288_grf *grf, uint channel,
198 bool enable, bool enable_bst, bool enable_odt)
199 {
200 uint mask;
201 bool disable_bst = !enable_bst;
202
203 mask = channel ?
204 (1 << LPDDR3_EN1_SHIFT | 1 << UPCTL1_BST_DIABLE_SHIFT |
205 1 << UPCTL1_LPDDR3_ODT_EN_SHIFT) :
206 (1 << LPDDR3_EN0_SHIFT | 1 << UPCTL0_BST_DIABLE_SHIFT |
207 1 << UPCTL0_LPDDR3_ODT_EN_SHIFT);
208 rk_clrsetreg(&grf->soc_con2, mask,
209 enable << (channel ? LPDDR3_EN1_SHIFT : LPDDR3_EN0_SHIFT) |
210 disable_bst << (channel ? UPCTL1_BST_DIABLE_SHIFT :
211 UPCTL0_BST_DIABLE_SHIFT) |
212 enable_odt << (channel ? UPCTL1_LPDDR3_ODT_EN_SHIFT :
213 UPCTL0_LPDDR3_ODT_EN_SHIFT));
214 }
215
216 static void pctl_cfg(u32 channel, struct rk3288_ddr_pctl *pctl,
217 const struct rk3288_sdram_params *sdram_params,
218 struct rk3288_grf *grf)
219 {
220 unsigned int burstlen;
221
222 burstlen = (sdram_params->base.noc_timing >> 18) & 0x7;
223 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u,
224 sizeof(sdram_params->pctl_timing));
225 switch (sdram_params->base.dramtype) {
226 case LPDDR3:
227 writel(sdram_params->pctl_timing.tcl - 1,
228 &pctl->dfitrddataen);
229 writel(sdram_params->pctl_timing.tcwl,
230 &pctl->dfitphywrlat);
231 burstlen >>= 1;
232 writel(LPDDR2_S4 | 0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT |
233 LPDDR2_EN | burstlen << BURSTLENGTH_SHIFT |
234 (6 - 4) << TFAW_SHIFT | PD_EXIT_FAST |
235 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,
236 &pctl->mcfg);
237 ddr_set_ddr3_mode(grf, channel, false);
238 ddr_set_enable(grf, channel, true);
239 ddr_set_en_bst_odt(grf, channel, true, false,
240 sdram_params->base.odt);
241 break;
242 case DDR3:
243 if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) {
244 writel(sdram_params->pctl_timing.tcl - 3,
245 &pctl->dfitrddataen);
246 } else {
247 writel(sdram_params->pctl_timing.tcl - 2,
248 &pctl->dfitrddataen);
249 }
250 writel(sdram_params->pctl_timing.tcwl - 1,
251 &pctl->dfitphywrlat);
252 writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN |
253 DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW |
254 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,
255 &pctl->mcfg);
256 ddr_set_ddr3_mode(grf, channel, true);
257 ddr_set_enable(grf, channel, true);
258
259 ddr_set_en_bst_odt(grf, channel, false, true, false);
260 break;
261 }
262
263 setbits_le32(&pctl->scfg, 1);
264 }
265
266 static void phy_cfg(const struct chan_info *chan, u32 channel,
267 const struct rk3288_sdram_params *sdram_params)
268 {
269 struct rk3288_ddr_publ *publ = chan->publ;
270 struct rk3288_msch *msch = chan->msch;
271 uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000;
272 u32 dinit2, tmp;
273 int i;
274
275 dinit2 = DIV_ROUND_UP(ddr_freq_mhz * 200000, 1000);
276 /* DDR PHY Timing */
277 copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0,
278 sizeof(sdram_params->phy_timing));
279 writel(sdram_params->base.noc_timing, &msch->ddrtiming);
280 writel(0x3f, &msch->readlatency);
281 writel(sdram_params->base.noc_activate, &msch->activate);
282 writel(2 << BUSWRTORD_SHIFT | 2 << BUSRDTOWR_SHIFT |
283 1 << BUSRDTORD_SHIFT, &msch->devtodev);
284 writel(DIV_ROUND_UP(ddr_freq_mhz * 5120, 1000) << PRT_DLLLOCK_SHIFT |
285 DIV_ROUND_UP(ddr_freq_mhz * 50, 1000) << PRT_DLLSRST_SHIFT |
286 8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]);
287 writel(DIV_ROUND_UP(ddr_freq_mhz * 500000, 1000) << PRT_DINIT0_SHIFT |
288 DIV_ROUND_UP(ddr_freq_mhz * 400, 1000) << PRT_DINIT1_SHIFT,
289 &publ->ptr[1]);
290 writel(min(dinit2, 0x1ffffU) << PRT_DINIT2_SHIFT |
291 DIV_ROUND_UP(ddr_freq_mhz * 1000, 1000) << PRT_DINIT3_SHIFT,
292 &publ->ptr[2]);
293
294 switch (sdram_params->base.dramtype) {
295 case LPDDR3:
296 clrsetbits_le32(&publ->pgcr, 0x1F,
297 0 << PGCR_DFTLMT_SHIFT |
298 0 << PGCR_DFTCMP_SHIFT |
299 1 << PGCR_DQSCFG_SHIFT |
300 0 << PGCR_ITMDMD_SHIFT);
301 /* DDRMODE select LPDDR3 */
302 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT,
303 DDRMD_LPDDR2_LPDDR3 << DDRMD_SHIFT);
304 clrsetbits_le32(&publ->dxccr,
305 DQSNRES_MASK << DQSNRES_SHIFT |
306 DQSRES_MASK << DQSRES_SHIFT,
307 4 << DQSRES_SHIFT | 0xc << DQSNRES_SHIFT);
308 tmp = readl(&publ->dtpr[1]);
309 tmp = ((tmp >> TDQSCKMAX_SHIFT) & TDQSCKMAX_MASK) -
310 ((tmp >> TDQSCK_SHIFT) & TDQSCK_MASK);
311 clrsetbits_le32(&publ->dsgcr,
312 DQSGE_MASK << DQSGE_SHIFT |
313 DQSGX_MASK << DQSGX_SHIFT,
314 tmp << DQSGE_SHIFT | tmp << DQSGX_SHIFT);
315 break;
316 case DDR3:
317 clrbits_le32(&publ->pgcr, 0x1f);
318 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT,
319 DDRMD_DDR3 << DDRMD_SHIFT);
320 break;
321 }
322 if (sdram_params->base.odt) {
323 /*dynamic RTT enable */
324 for (i = 0; i < 4; i++)
325 setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
326 } else {
327 /*dynamic RTT disable */
328 for (i = 0; i < 4; i++)
329 clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
330 }
331 }
332
333 static void phy_init(struct rk3288_ddr_publ *publ)
334 {
335 setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST
336 | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR);
337 udelay(1);
338 while ((readl(&publ->pgsr) &
339 (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) !=
340 (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE))
341 ;
342 }
343
344 static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank,
345 u32 cmd, u32 arg)
346 {
347 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
348 udelay(1);
349 while (readl(&pctl->mcmd) & START_CMD)
350 ;
351 }
352
353 static inline void send_command_op(struct rk3288_ddr_pctl *pctl,
354 u32 rank, u32 cmd, u32 ma, u32 op)
355 {
356 send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT |
357 (op & LPDDR2_OP_MASK) << LPDDR2_OP_SHIFT);
358 }
359
360 static void memory_init(struct rk3288_ddr_publ *publ,
361 u32 dramtype)
362 {
363 setbits_le32(&publ->pir,
364 (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP
365 | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC
366 | (dramtype == DDR3 ? PIR_DRAMRST : 0)));
367 udelay(1);
368 while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE))
369 != (PGSR_IDONE | PGSR_DLDONE))
370 ;
371 }
372
373 static void move_to_config_state(struct rk3288_ddr_publ *publ,
374 struct rk3288_ddr_pctl *pctl)
375 {
376 unsigned int state;
377
378 while (1) {
379 state = readl(&pctl->stat) & PCTL_STAT_MSK;
380
381 switch (state) {
382 case LOW_POWER:
383 writel(WAKEUP_STATE, &pctl->sctl);
384 while ((readl(&pctl->stat) & PCTL_STAT_MSK)
385 != ACCESS)
386 ;
387 /* wait DLL lock */
388 while ((readl(&publ->pgsr) & PGSR_DLDONE)
389 != PGSR_DLDONE)
390 ;
391 /* if at low power state,need wakeup first,
392 * and then enter the config
393 * so here no break.
394 */
395 case ACCESS:
396 /* no break */
397 case INIT_MEM:
398 writel(CFG_STATE, &pctl->sctl);
399 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
400 ;
401 break;
402 case CONFIG:
403 return;
404 default:
405 break;
406 }
407 }
408 }
409
410 static void set_bandwidth_ratio(const struct chan_info *chan, u32 channel,
411 u32 n, struct rk3288_grf *grf)
412 {
413 struct rk3288_ddr_pctl *pctl = chan->pctl;
414 struct rk3288_ddr_publ *publ = chan->publ;
415 struct rk3288_msch *msch = chan->msch;
416
417 if (n == 1) {
418 setbits_le32(&pctl->ppcfg, 1);
419 rk_setreg(&grf->soc_con0, 1 << (8 + channel));
420 setbits_le32(&msch->ddrtiming, 1 << 31);
421 /* Data Byte disable*/
422 clrbits_le32(&publ->datx8[2].dxgcr, 1);
423 clrbits_le32(&publ->datx8[3].dxgcr, 1);
424 /* disable DLL */
425 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
426 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
427 } else {
428 clrbits_le32(&pctl->ppcfg, 1);
429 rk_clrreg(&grf->soc_con0, 1 << (8 + channel));
430 clrbits_le32(&msch->ddrtiming, 1 << 31);
431 /* Data Byte enable*/
432 setbits_le32(&publ->datx8[2].dxgcr, 1);
433 setbits_le32(&publ->datx8[3].dxgcr, 1);
434
435 /* enable DLL */
436 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
437 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
438 /* reset DLL */
439 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
440 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
441 udelay(10);
442 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
443 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
444 }
445 setbits_le32(&pctl->dfistcfg0, 1 << 2);
446 }
447
448 static int data_training(const struct chan_info *chan, u32 channel,
449 const struct rk3288_sdram_params *sdram_params)
450 {
451 unsigned int j;
452 int ret = 0;
453 u32 rank;
454 int i;
455 u32 step[2] = { PIR_QSTRN, PIR_RVTRN };
456 struct rk3288_ddr_publ *publ = chan->publ;
457 struct rk3288_ddr_pctl *pctl = chan->pctl;
458
459 /* disable auto refresh */
460 writel(0, &pctl->trefi);
461
462 if (sdram_params->base.dramtype != LPDDR3)
463 setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
464 rank = sdram_params->ch[channel].rank | 1;
465 for (j = 0; j < ARRAY_SIZE(step); j++) {
466 /*
467 * trigger QSTRN and RVTRN
468 * clear DTDONE status
469 */
470 setbits_le32(&publ->pir, PIR_CLRSR);
471
472 /* trigger DTT */
473 setbits_le32(&publ->pir,
474 PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP |
475 PIR_CLRSR);
476 udelay(1);
477 /* wait echo byte DTDONE */
478 while ((readl(&publ->datx8[0].dxgsr[0]) & rank)
479 != rank)
480 ;
481 while ((readl(&publ->datx8[1].dxgsr[0]) & rank)
482 != rank)
483 ;
484 if (!(readl(&pctl->ppcfg) & 1)) {
485 while ((readl(&publ->datx8[2].dxgsr[0])
486 & rank) != rank)
487 ;
488 while ((readl(&publ->datx8[3].dxgsr[0])
489 & rank) != rank)
490 ;
491 }
492 if (readl(&publ->pgsr) &
493 (PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) {
494 ret = -1;
495 break;
496 }
497 }
498 /* send some auto refresh to complement the lost while DTT */
499 for (i = 0; i < (rank > 1 ? 8 : 4); i++)
500 send_command(pctl, rank, REF_CMD, 0);
501
502 if (sdram_params->base.dramtype != LPDDR3)
503 clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
504
505 /* resume auto refresh */
506 writel(sdram_params->pctl_timing.trefi, &pctl->trefi);
507
508 return ret;
509 }
510
511 static void move_to_access_state(const struct chan_info *chan)
512 {
513 struct rk3288_ddr_publ *publ = chan->publ;
514 struct rk3288_ddr_pctl *pctl = chan->pctl;
515 unsigned int state;
516
517 while (1) {
518 state = readl(&pctl->stat) & PCTL_STAT_MSK;
519
520 switch (state) {
521 case LOW_POWER:
522 if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
523 LP_TRIG_MASK) == 1)
524 return;
525
526 writel(WAKEUP_STATE, &pctl->sctl);
527 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
528 ;
529 /* wait DLL lock */
530 while ((readl(&publ->pgsr) & PGSR_DLDONE)
531 != PGSR_DLDONE)
532 ;
533 break;
534 case INIT_MEM:
535 writel(CFG_STATE, &pctl->sctl);
536 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
537 ;
538 case CONFIG:
539 writel(GO_STATE, &pctl->sctl);
540 while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
541 ;
542 break;
543 case ACCESS:
544 return;
545 default:
546 break;
547 }
548 }
549 }
550
551 static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum,
552 const struct rk3288_sdram_params *sdram_params)
553 {
554 struct rk3288_ddr_publ *publ = chan->publ;
555
556 if (sdram_params->ch[chnum].bk == 3)
557 clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT,
558 1 << PDQ_SHIFT);
559 else
560 clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT);
561
562 writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf);
563 }
564
565 static void dram_all_config(const struct dram_info *dram,
566 const struct rk3288_sdram_params *sdram_params)
567 {
568 unsigned int chan;
569 u32 sys_reg = 0;
570
571 sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
572 sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT;
573 for (chan = 0; chan < sdram_params->num_channels; chan++) {
574 const struct rk3288_sdram_channel *info =
575 &sdram_params->ch[chan];
576
577 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
578 sys_reg |= chan << SYS_REG_CHINFO_SHIFT(chan);
579 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
580 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
581 sys_reg |= info->bk == 3 ? 1 << SYS_REG_BK_SHIFT(chan) : 0;
582 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
583 sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
584 sys_reg |= info->bw << SYS_REG_BW_SHIFT(chan);
585 sys_reg |= info->dbw << SYS_REG_DBW_SHIFT(chan);
586
587 dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
588 }
589 writel(sys_reg, &dram->pmu->sys_reg[2]);
590 rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride);
591 }
592
593 static int sdram_init(struct dram_info *dram,
594 const struct rk3288_sdram_params *sdram_params)
595 {
596 int channel;
597 int zqcr;
598 int ret;
599
600 debug("%s start\n", __func__);
601 if ((sdram_params->base.dramtype == DDR3 &&
602 sdram_params->base.ddr_freq > 800000000) ||
603 (sdram_params->base.dramtype == LPDDR3 &&
604 sdram_params->base.ddr_freq > 533000000)) {
605 debug("SDRAM frequency is too high!");
606 return -E2BIG;
607 }
608
609 debug("ddr clk dpll\n");
610 ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq);
611 debug("ret=%d\n", ret);
612 if (ret) {
613 debug("Could not set DDR clock\n");
614 return ret;
615 }
616
617 for (channel = 0; channel < 2; channel++) {
618 const struct chan_info *chan = &dram->chan[channel];
619 struct rk3288_ddr_pctl *pctl = chan->pctl;
620 struct rk3288_ddr_publ *publ = chan->publ;
621
622 phy_pctrl_reset(dram->cru, publ, channel);
623 phy_dll_bypass_set(publ, sdram_params->base.ddr_freq);
624
625 if (channel >= sdram_params->num_channels)
626 continue;
627
628 dfi_cfg(pctl, sdram_params->base.dramtype);
629
630 pctl_cfg(channel, pctl, sdram_params, dram->grf);
631
632 phy_cfg(chan, channel, sdram_params);
633
634 phy_init(publ);
635
636 writel(POWER_UP_START, &pctl->powctl);
637 while (!(readl(&pctl->powstat) & POWER_UP_DONE))
638 ;
639
640 memory_init(publ, sdram_params->base.dramtype);
641 move_to_config_state(publ, pctl);
642
643 if (sdram_params->base.dramtype == LPDDR3) {
644 send_command(pctl, 3, DESELECT_CMD, 0);
645 udelay(1);
646 send_command(pctl, 3, PREA_CMD, 0);
647 udelay(1);
648 send_command_op(pctl, 3, MRS_CMD, 63, 0xfc);
649 udelay(1);
650 send_command_op(pctl, 3, MRS_CMD, 1,
651 sdram_params->phy_timing.mr[1]);
652 udelay(1);
653 send_command_op(pctl, 3, MRS_CMD, 2,
654 sdram_params->phy_timing.mr[2]);
655 udelay(1);
656 send_command_op(pctl, 3, MRS_CMD, 3,
657 sdram_params->phy_timing.mr[3]);
658 udelay(1);
659 }
660
661 set_bandwidth_ratio(chan, channel,
662 sdram_params->ch[channel].bw, dram->grf);
663 /*
664 * set cs
665 * CS0, n=1
666 * CS1, n=2
667 * CS0 & CS1, n = 3
668 */
669 clrsetbits_le32(&publ->pgcr, 0xF << 18,
670 (sdram_params->ch[channel].rank | 1) << 18);
671 /* DS=40ohm,ODT=155ohm */
672 zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT |
673 2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT |
674 0x19 << PD_OUTPUT_SHIFT;
675 writel(zqcr, &publ->zq1cr[0]);
676 writel(zqcr, &publ->zq0cr[0]);
677
678 if (sdram_params->base.dramtype == LPDDR3) {
679 /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
680 udelay(10);
681 send_command_op(pctl,
682 sdram_params->ch[channel].rank | 1,
683 MRS_CMD, 11,
684 sdram_params->base.odt ? 3 : 0);
685 if (channel == 0) {
686 writel(0, &pctl->mrrcfg0);
687 send_command_op(pctl, 1, MRR_CMD, 8, 0);
688 /* S8 */
689 if ((readl(&pctl->mrrstat0) & 0x3) != 3) {
690 debug("failed!");
691 return -EREMOTEIO;
692 }
693 }
694 }
695
696 if (-1 == data_training(chan, channel, sdram_params)) {
697 if (sdram_params->base.dramtype == LPDDR3) {
698 ddr_phy_ctl_reset(dram->cru, channel, 1);
699 udelay(10);
700 ddr_phy_ctl_reset(dram->cru, channel, 0);
701 udelay(10);
702 }
703 debug("failed!");
704 return -EIO;
705 }
706
707 if (sdram_params->base.dramtype == LPDDR3) {
708 u32 i;
709 writel(0, &pctl->mrrcfg0);
710 for (i = 0; i < 17; i++)
711 send_command_op(pctl, 1, MRR_CMD, i, 0);
712 }
713 move_to_access_state(chan);
714 }
715 dram_all_config(dram, sdram_params);
716 debug("%s done\n", __func__);
717
718 return 0;
719 }
720 #endif /* CONFIG_SPL_BUILD */
721
722 size_t sdram_size_mb(struct rk3288_pmu *pmu)
723 {
724 u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4;
725 size_t chipsize_mb = 0;
726 size_t size_mb = 0;
727 u32 ch;
728 u32 sys_reg = readl(&pmu->sys_reg[2]);
729 u32 chans;
730
731 chans = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK);
732
733 for (ch = 0; ch < chans; ch++) {
734 rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) &
735 SYS_REG_RANK_MASK);
736 col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK);
737 bk = sys_reg & (1 << SYS_REG_BK_SHIFT(ch)) ? 3 : 0;
738 cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) &
739 SYS_REG_CS0_ROW_MASK);
740 cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) &
741 SYS_REG_CS1_ROW_MASK);
742 bw = (sys_reg >> SYS_REG_BW_SHIFT(ch)) &
743 SYS_REG_BW_MASK;
744 row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) &
745 SYS_REG_ROW_3_4_MASK;
746
747 chipsize_mb = (1 << (cs0_row + col + bk + bw - 20));
748
749 if (rank > 1)
750 chipsize_mb += chipsize_mb >>
751 (cs0_row - cs1_row);
752 if (row_3_4)
753 chipsize_mb = chipsize_mb * 3 / 4;
754 size_mb += chipsize_mb;
755 }
756
757 /*
758 * we use the 0x00000000~0xfeffffff space since 0xff000000~0xffffffff
759 * is SoC register space (i.e. reserved)
760 */
761 size_mb = min(size_mb, 0xff000000 >> 20);
762
763 return size_mb;
764 }
765
766 #ifdef CONFIG_SPL_BUILD
767 # ifdef CONFIG_ROCKCHIP_FAST_SPL
768 static int veyron_init(struct dram_info *priv)
769 {
770 struct udevice *pmic;
771 int ret;
772
773 ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
774 if (ret)
775 return ret;
776
777 /* Slowly raise to max CPU voltage to prevent overshoot */
778 ret = rk808_spl_configure_buck(pmic, 1, 1200000);
779 if (ret)
780 return ret;
781 udelay(175);/* Must wait for voltage to stabilize, 2mV/us */
782 ret = rk808_spl_configure_buck(pmic, 1, 1400000);
783 if (ret)
784 return ret;
785 udelay(100);/* Must wait for voltage to stabilize, 2mV/us */
786
787 rk3288_clk_configure_cpu(priv->cru, priv->grf);
788
789 return 0;
790 }
791 # endif
792
793 static int setup_sdram(struct udevice *dev)
794 {
795 struct dram_info *priv = dev_get_priv(dev);
796 struct rk3288_sdram_params *params = dev_get_platdata(dev);
797
798 # ifdef CONFIG_ROCKCHIP_FAST_SPL
799 if (priv->is_veyron) {
800 int ret;
801
802 ret = veyron_init(priv);
803 if (ret)
804 return ret;
805 }
806 # endif
807
808 return sdram_init(priv, params);
809 }
810
811 static int rk3288_dmc_ofdata_to_platdata(struct udevice *dev)
812 {
813 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
814 struct rk3288_sdram_params *params = dev_get_platdata(dev);
815 const void *blob = gd->fdt_blob;
816 int node = dev->of_offset;
817 int i, ret;
818
819 params->num_channels = fdtdec_get_int(blob, node,
820 "rockchip,num-channels", 1);
821 for (i = 0; i < params->num_channels; i++) {
822 ret = fdtdec_get_byte_array(blob, node,
823 "rockchip,sdram-channel",
824 (u8 *)&params->ch[i],
825 sizeof(params->ch[i]));
826 if (ret) {
827 debug("%s: Cannot read rockchip,sdram-channel\n",
828 __func__);
829 return -EINVAL;
830 }
831 }
832 ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing",
833 (u32 *)&params->pctl_timing,
834 sizeof(params->pctl_timing) / sizeof(u32));
835 if (ret) {
836 debug("%s: Cannot read rockchip,pctl-timing\n", __func__);
837 return -EINVAL;
838 }
839 ret = fdtdec_get_int_array(blob, node, "rockchip,phy-timing",
840 (u32 *)&params->phy_timing,
841 sizeof(params->phy_timing) / sizeof(u32));
842 if (ret) {
843 debug("%s: Cannot read rockchip,phy-timing\n", __func__);
844 return -EINVAL;
845 }
846 ret = fdtdec_get_int_array(blob, node, "rockchip,sdram-params",
847 (u32 *)&params->base,
848 sizeof(params->base) / sizeof(u32));
849 if (ret) {
850 debug("%s: Cannot read rockchip,sdram-params\n", __func__);
851 return -EINVAL;
852 }
853 #ifdef CONFIG_ROCKCHIP_FAST_SPL
854 struct dram_info *priv = dev_get_priv(dev);
855
856 priv->is_veyron = !fdt_node_check_compatible(blob, 0, "google,veyron");
857 #endif
858 ret = regmap_init_mem(dev, &params->map);
859 if (ret)
860 return ret;
861 #endif
862
863 return 0;
864 }
865 #endif /* CONFIG_SPL_BUILD */
866
867 #if CONFIG_IS_ENABLED(OF_PLATDATA)
868 static int conv_of_platdata(struct udevice *dev)
869 {
870 struct rk3288_sdram_params *plat = dev_get_platdata(dev);
871 struct dtd_rockchip_rk3288_dmc *of_plat = &plat->of_plat;
872 int i, ret;
873
874 for (i = 0; i < 2; i++) {
875 memcpy(&plat->ch[i], of_plat->rockchip_sdram_channel,
876 sizeof(plat->ch[i]));
877 }
878 memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing,
879 sizeof(plat->pctl_timing));
880 memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing,
881 sizeof(plat->phy_timing));
882 memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
883 plat->num_channels = of_plat->rockchip_num_channels;
884 ret = regmap_init_mem_platdata(dev, of_plat->reg,
885 ARRAY_SIZE(of_plat->reg) / 2,
886 &plat->map);
887 if (ret)
888 return ret;
889
890 return 0;
891 }
892 #endif
893
894 static int rk3288_dmc_probe(struct udevice *dev)
895 {
896 #ifdef CONFIG_SPL_BUILD
897 struct rk3288_sdram_params *plat = dev_get_platdata(dev);
898 #endif
899 struct dram_info *priv = dev_get_priv(dev);
900 struct regmap *map;
901 int ret;
902 struct udevice *dev_clk;
903
904 #if CONFIG_IS_ENABLED(OF_PLATDATA)
905 ret = conv_of_platdata(dev);
906 if (ret)
907 return ret;
908 #endif
909 map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC);
910 if (IS_ERR(map))
911 return PTR_ERR(map);
912 priv->chan[0].msch = regmap_get_range(map, 0);
913 priv->chan[1].msch = (struct rk3288_msch *)
914 (regmap_get_range(map, 0) + 0x80);
915
916 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
917 priv->sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_SGRF);
918 priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
919
920 #ifdef CONFIG_SPL_BUILD
921 priv->chan[0].pctl = regmap_get_range(plat->map, 0);
922 priv->chan[0].publ = regmap_get_range(plat->map, 1);
923 priv->chan[1].pctl = regmap_get_range(plat->map, 2);
924 priv->chan[1].publ = regmap_get_range(plat->map, 3);
925 #endif
926 ret = rockchip_get_clk(&dev_clk);
927 if (ret)
928 return ret;
929 priv->ddr_clk.id = CLK_DDR;
930 ret = clk_request(dev_clk, &priv->ddr_clk);
931 if (ret)
932 return ret;
933
934 priv->cru = rockchip_get_cru();
935 if (IS_ERR(priv->cru))
936 return PTR_ERR(priv->cru);
937 #ifdef CONFIG_SPL_BUILD
938 ret = setup_sdram(dev);
939 if (ret)
940 return ret;
941 #endif
942 priv->info.base = 0;
943 priv->info.size = sdram_size_mb(priv->pmu) << 20;
944
945 return 0;
946 }
947
948 static int rk3288_dmc_get_info(struct udevice *dev, struct ram_info *info)
949 {
950 struct dram_info *priv = dev_get_priv(dev);
951
952 *info = priv->info;
953
954 return 0;
955 }
956
957 static struct ram_ops rk3288_dmc_ops = {
958 .get_info = rk3288_dmc_get_info,
959 };
960
961 static const struct udevice_id rk3288_dmc_ids[] = {
962 { .compatible = "rockchip,rk3288-dmc" },
963 { }
964 };
965
966 U_BOOT_DRIVER(dmc_rk3288) = {
967 .name = "rockchip_rk3288_dmc",
968 .id = UCLASS_RAM,
969 .of_match = rk3288_dmc_ids,
970 .ops = &rk3288_dmc_ops,
971 #ifdef CONFIG_SPL_BUILD
972 .ofdata_to_platdata = rk3288_dmc_ofdata_to_platdata,
973 #endif
974 .probe = rk3288_dmc_probe,
975 .priv_auto_alloc_size = sizeof(struct dram_info),
976 #ifdef CONFIG_SPL_BUILD
977 .platdata_auto_alloc_size = sizeof(struct rk3288_sdram_params),
978 #endif
979 };
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