]>
git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arm/mach-socfpga/clock_manager.c
2 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock_manager.h>
12 DECLARE_GLOBAL_DATA_PTR
;
14 static const struct socfpga_clock_manager
*clock_manager_base
=
15 (struct socfpga_clock_manager
*)SOCFPGA_CLKMGR_ADDRESS
;
17 void cm_wait_for_lock(u32 mask
)
22 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
23 inter_val
= readl(&clock_manager_base
->inter
) & mask
;
24 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
25 inter_val
= readl(&clock_manager_base
->stat
) & mask
;
27 /* Wait for stable lock */
28 if (inter_val
== mask
)
37 /* function to poll in the fsm busy bit */
38 int cm_wait_for_fsm(void)
40 return wait_for_bit_le32(&clock_manager_base
->stat
,
41 CLKMGR_STAT_BUSY
, false, 20000, false);
44 int set_cpu_clk_info(void)
46 /* Calculate the clock frequencies required for drivers */
47 cm_get_l4_sp_clk_hz();
48 cm_get_mmc_controller_clk_hz();
50 gd
->bd
->bi_arm_freq
= cm_get_mpu_clk_hz() / 1000000;
51 gd
->bd
->bi_dsp_freq
= 0;
53 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
54 gd
->bd
->bi_ddr_freq
= cm_get_sdram_clk_hz() / 1000000;
55 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
56 gd
->bd
->bi_ddr_freq
= 0;
62 int do_showclocks(cmd_tbl_t
*cmdtp
, int flag
, int argc
, char * const argv
[])
64 cm_print_clock_quick_summary();
69 clocks
, CONFIG_SYS_MAXARGS
, 1, do_showclocks
,