arch/arm/mach-socfpga/spl.c

   1 /*
   2  *  Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/pl310.h>
  10 #include <asm/u-boot.h>
  11 #include <asm/utils.h>
  12 #include <image.h>
  13 #include <asm/arch/reset_manager.h>
  14 #include <spl.h>
  15 #include <asm/arch/system_manager.h>
  16 #include <asm/arch/freeze_controller.h>
  17 #include <asm/arch/clock_manager.h>
  18 #include <asm/arch/scan_manager.h>
  19 #include <asm/arch/sdram.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 static struct pl310_regs *const pl310 =
  24         (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  25
  26 void board_init_f(ulong dummy)
  27 {
  28         struct socfpga_system_manager *sysmgr_regs =
  29                 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  30         unsigned long reg;
  31         /*
  32          * First C code to run. Clear fake OCRAM ECC first as SBE
  33          * and DBE might triggered during power on
  34          */
  35         reg = readl(&sysmgr_regs->eccgrp_ocram);
  36         if (reg & SYSMGR_ECC_OCRAM_SERR)
  37                 writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
  38                        &sysmgr_regs->eccgrp_ocram);
  39         if (reg & SYSMGR_ECC_OCRAM_DERR)
  40                 writel(SYSMGR_ECC_OCRAM_DERR  | SYSMGR_ECC_OCRAM_EN,
  41                        &sysmgr_regs->eccgrp_ocram);
  42
  43         memset(__bss_start, 0, __bss_end - __bss_start);
  44
  45         /* Remap SDRAM to 0x0 */
  46         writel(0x1, &pl310->pl310_addr_filter_start);
  47
  48         board_init_r(NULL, 0);
  49 }
  50
  51 u32 spl_boot_device(void)
  52 {
  53         return BOOT_DEVICE_RAM;
  54 }
  55
  56 /*
  57  * Board initialization after bss clearance
  58  */
  59 void spl_board_init(void)
  60 {
  61         unsigned long sdram_size;
  62 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
  63         const struct cm_config *cm_default_cfg = cm_get_default_config();
  64 #endif
  65
  66         debug("Freezing all I/O banks\n");
  67         /* freeze all IO banks */
  68         sys_mgr_frzctrl_freeze_req();
  69
  70         socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
  71         socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
  72         socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
  73
  74         timer_init();
  75
  76         debug("Reconfigure Clock Manager\n");
  77         /* reconfigure the PLLs */
  78         cm_basic_init(cm_default_cfg);
  79
  80         /* Enable bootrom to configure IOs. */
  81         sysmgr_enable_warmrstcfgio();
  82
  83         /* configure the IOCSR / IO buffer settings */
  84         if (scan_mgr_configure_iocsr())
  85                 hang();
  86
  87         /* configure the pin muxing through system manager */
  88         sysmgr_pinmux_init();
  89 #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
  90
  91         /* de-assert reset for peripherals and bridges based on handoff */
  92         reset_deassert_peripherals_handoff();
  93
  94         debug("Unfreezing/Thaw all I/O banks\n");
  95         /* unfreeze / thaw all IO banks */
  96         sys_mgr_frzctrl_thaw_req();
  97
  98         /* enable console uart printing */
  99         preloader_console_init();
 100
 101         if (sdram_mmr_init_full(0xffffffff) != 0) {
 102                 puts("SDRAM init failed.\n");
 103                 hang();
 104         }
 105
 106         debug("SDRAM: Calibrating PHY\n");
 107         /* SDRAM calibration */
 108         if (sdram_calibration_full() == 0) {
 109                 puts("SDRAM calibration failed.\n");
 110                 hang();
 111         }
 112
 113         sdram_size = sdram_calculate_size();
 114         debug("SDRAM: %ld MiB\n", sdram_size >> 20);
 115
 116         /* Sanity check ensure correct SDRAM size specified */
 117         if (get_ram_size(0, sdram_size) != sdram_size) {
 118                 puts("SDRAM size check failed!\n");
 119                 hang();
 120         }
 121 }