arch/arm/mach-stm32/stm32f4/clock.c

   1 /*
   2  * (C) Copyright 2015
   3  * Kamil Lulko, <kamil.lulko@gmail.com>
   4  *
   5  * (C) Copyright 2014
   6  * STMicroelectronics
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/stm32.h>
  14 #include <asm/arch/stm32_periph.h>
  15
  16 #define RCC_CR_HSION            (1 << 0)
  17 #define RCC_CR_HSEON            (1 << 16)
  18 #define RCC_CR_HSERDY           (1 << 17)
  19 #define RCC_CR_HSEBYP           (1 << 18)
  20 #define RCC_CR_CSSON            (1 << 19)
  21 #define RCC_CR_PLLON            (1 << 24)
  22 #define RCC_CR_PLLRDY           (1 << 25)
  23
  24 #define RCC_PLLCFGR_PLLM_MASK   0x3F
  25 #define RCC_PLLCFGR_PLLN_MASK   0x7FC0
  26 #define RCC_PLLCFGR_PLLP_MASK   0x30000
  27 #define RCC_PLLCFGR_PLLQ_MASK   0xF000000
  28 #define RCC_PLLCFGR_PLLSRC      (1 << 22)
  29 #define RCC_PLLCFGR_PLLN_SHIFT  6
  30 #define RCC_PLLCFGR_PLLP_SHIFT  16
  31 #define RCC_PLLCFGR_PLLQ_SHIFT  24
  32
  33 #define RCC_CFGR_AHB_PSC_MASK   0xF0
  34 #define RCC_CFGR_APB1_PSC_MASK  0x1C00
  35 #define RCC_CFGR_APB2_PSC_MASK  0xE000
  36 #define RCC_CFGR_SW0            (1 << 0)
  37 #define RCC_CFGR_SW1            (1 << 1)
  38 #define RCC_CFGR_SW_MASK        0x3
  39 #define RCC_CFGR_SW_HSI         0
  40 #define RCC_CFGR_SW_HSE         RCC_CFGR_SW0
  41 #define RCC_CFGR_SW_PLL         RCC_CFGR_SW1
  42 #define RCC_CFGR_SWS0           (1 << 2)
  43 #define RCC_CFGR_SWS1           (1 << 3)
  44 #define RCC_CFGR_SWS_MASK       0xC
  45 #define RCC_CFGR_SWS_HSI        0
  46 #define RCC_CFGR_SWS_HSE        RCC_CFGR_SWS0
  47 #define RCC_CFGR_SWS_PLL        RCC_CFGR_SWS1
  48 #define RCC_CFGR_HPRE_SHIFT     4
  49 #define RCC_CFGR_PPRE1_SHIFT    10
  50 #define RCC_CFGR_PPRE2_SHIFT    13
  51
  52 #define RCC_APB1ENR_PWREN       (1 << 28)
  53
  54 /*
  55  * RCC USART specific definitions
  56  */
  57 #define RCC_ENR_USART1EN                (1 << 4)
  58 #define RCC_ENR_USART2EN                (1 << 17)
  59 #define RCC_ENR_USART3EN                (1 << 18)
  60 #define RCC_ENR_USART6EN                (1 <<  5)
  61
  62 #define PWR_CR_VOS0             (1 << 14)
  63 #define PWR_CR_VOS1             (1 << 15)
  64 #define PWR_CR_VOS_MASK         0xC000
  65 #define PWR_CR_VOS_SCALE_MODE_1 (PWR_CR_VOS0 | PWR_CR_VOS1)
  66 #define PWR_CR_VOS_SCALE_MODE_2 (PWR_CR_VOS1)
  67 #define PWR_CR_VOS_SCALE_MODE_3 (PWR_CR_VOS0)
  68
  69 /*
  70  * RCC GPIO specific definitions
  71  */
  72 #define RCC_ENR_GPIO_A_EN       (1 << 0)
  73 #define RCC_ENR_GPIO_B_EN       (1 << 1)
  74 #define RCC_ENR_GPIO_C_EN       (1 << 2)
  75 #define RCC_ENR_GPIO_D_EN       (1 << 3)
  76 #define RCC_ENR_GPIO_E_EN       (1 << 4)
  77 #define RCC_ENR_GPIO_F_EN       (1 << 5)
  78 #define RCC_ENR_GPIO_G_EN       (1 << 6)
  79 #define RCC_ENR_GPIO_H_EN       (1 << 7)
  80 #define RCC_ENR_GPIO_I_EN       (1 << 8)
  81 #define RCC_ENR_GPIO_J_EN       (1 << 9)
  82 #define RCC_ENR_GPIO_K_EN       (1 << 10)
  83
  84 struct pll_psc {
  85         u8      pll_m;
  86         u16     pll_n;
  87         u8      pll_p;
  88         u8      pll_q;
  89         u8      ahb_psc;
  90         u8      apb1_psc;
  91         u8      apb2_psc;
  92 };
  93
  94 #define AHB_PSC_1               0
  95 #define AHB_PSC_2               0x8
  96 #define AHB_PSC_4               0x9
  97 #define AHB_PSC_8               0xA
  98 #define AHB_PSC_16              0xB
  99 #define AHB_PSC_64              0xC
 100 #define AHB_PSC_128             0xD
 101 #define AHB_PSC_256             0xE
 102 #define AHB_PSC_512             0xF
 103
 104 #define APB_PSC_1               0
 105 #define APB_PSC_2               0x4
 106 #define APB_PSC_4               0x5
 107 #define APB_PSC_8               0x6
 108 #define APB_PSC_16              0x7
 109
 110 #if !defined(CONFIG_STM32_HSE_HZ)
 111 #error "CONFIG_STM32_HSE_HZ not defined!"
 112 #else
 113 #if (CONFIG_STM32_HSE_HZ == 8000000)
 114 #if (CONFIG_SYS_CLK_FREQ == 180000000)
 115 /* 180 MHz */
 116 struct pll_psc sys_pll_psc = {
 117         .pll_m = 8,
 118         .pll_n = 360,
 119         .pll_p = 2,
 120         .pll_q = 8,
 121         .ahb_psc = AHB_PSC_1,
 122         .apb1_psc = APB_PSC_4,
 123         .apb2_psc = APB_PSC_2
 124 };
 125 #else
 126 /* default 168 MHz */
 127 struct pll_psc sys_pll_psc = {
 128         .pll_m = 8,
 129         .pll_n = 336,
 130         .pll_p = 2,
 131         .pll_q = 7,
 132         .ahb_psc = AHB_PSC_1,
 133         .apb1_psc = APB_PSC_4,
 134         .apb2_psc = APB_PSC_2
 135 };
 136 #endif
 137 #else
 138 #error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
 139 #endif
 140 #endif
 141
 142 int configure_clocks(void)
 143 {
 144         /* Reset RCC configuration */
 145         setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
 146         writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
 147         clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON
 148                 | RCC_CR_PLLON));
 149         writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */
 150         clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
 151         writel(0, &STM32_RCC->cir); /* Disable all interrupts */
 152
 153         /* Configure for HSE+PLL operation */
 154         setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
 155         while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
 156                 ;
 157
 158         /* Enable high performance mode, System frequency up to 180 MHz */
 159         setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
 160         writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr);
 161
 162         setbits_le32(&STM32_RCC->cfgr, ((
 163                 sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
 164                 | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
 165                 | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
 166
 167         writel(sys_pll_psc.pll_m
 168                 | (sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT)
 169                 | (((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT)
 170                 | (sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT),
 171                 &STM32_RCC->pllcfgr);
 172         setbits_le32(&STM32_RCC->pllcfgr, RCC_PLLCFGR_PLLSRC);
 173
 174         setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);
 175
 176         while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
 177                 ;
 178
 179         stm32_flash_latency_cfg(5);
 180         clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
 181         setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
 182
 183         while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
 184                         RCC_CFGR_SWS_PLL)
 185                 ;
 186
 187         return 0;
 188 }
 189
 190 unsigned long clock_get(enum clock clck)
 191 {
 192         u32 sysclk = 0;
 193         u32 shift = 0;
 194         /* Prescaler table lookups for clock computation */
 195         u8 ahb_psc_table[16] = {
 196                 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
 197         };
 198         u8 apb_psc_table[8] = {
 199                 0, 0, 0, 0, 1, 2, 3, 4
 200         };
 201
 202         if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
 203                         RCC_CFGR_SWS_PLL) {
 204                 u16 pllm, plln, pllp;
 205                 pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
 206                 plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
 207                         >> RCC_PLLCFGR_PLLN_SHIFT);
 208                 pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
 209                         >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
 210                 sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
 211         }
 212
 213         switch (clck) {
 214         case CLOCK_CORE:
 215                 return sysclk;
 216                 break;
 217         case CLOCK_AHB:
 218                 shift = ahb_psc_table[(
 219                         (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
 220                         >> RCC_CFGR_HPRE_SHIFT)];
 221                 return sysclk >>= shift;
 222                 break;
 223         case CLOCK_APB1:
 224                 shift = apb_psc_table[(
 225                         (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
 226                         >> RCC_CFGR_PPRE1_SHIFT)];
 227                 return sysclk >>= shift;
 228                 break;
 229         case CLOCK_APB2:
 230                 shift = apb_psc_table[(
 231                         (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
 232                         >> RCC_CFGR_PPRE2_SHIFT)];
 233                 return sysclk >>= shift;
 234                 break;
 235         default:
 236                 return 0;
 237                 break;
 238         }
 239 }
 240
 241 void clock_setup(int peripheral)
 242 {
 243         switch (peripheral) {
 244         case USART1_CLOCK_CFG:
 245                 setbits_le32(&STM32_RCC->apb2enr, RCC_ENR_USART1EN);
 246                 break;
 247         case GPIO_A_CLOCK_CFG:
 248                 setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_A_EN);
 249                 break;
 250         case GPIO_B_CLOCK_CFG:
 251                 setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_B_EN);
 252                 break;
 253         case GPIO_C_CLOCK_CFG:
 254                 setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_C_EN);
 255                 break;
 256         case GPIO_D_CLOCK_CFG:
 257                 setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_D_EN);
 258                 break;
 259         case GPIO_E_CLOCK_CFG:
 260                 setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_E_EN);
 261                 break;
 262         case GPIO_F_CLOCK_CFG:
 263                 setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_F_EN);
 264                 break;
 265         case GPIO_G_CLOCK_CFG:
 266                 setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_G_EN);
 267                 break;
 268         case GPIO_H_CLOCK_CFG:
 269                 setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_H_EN);
 270                 break;
 271         case GPIO_I_CLOCK_CFG:
 272                 setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_I_EN);
 273                 break;
 274         case GPIO_J_CLOCK_CFG:
 275                 setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_J_EN);
 276                 break;
 277         case GPIO_K_CLOCK_CFG:
 278                 setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_K_EN);
 279                 break;
 280         default:
 281                 break;
 282         }
 283 }