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git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arm/mach-stm32/stm32f4/clock.c
3 * Kamil Lulko, <kamil.lulko@gmail.com>
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <stm32_rcc.h>
14 #include <asm/arch/stm32.h>
15 #include <asm/arch/stm32_periph.h>
17 #define RCC_CR_HSION (1 << 0)
18 #define RCC_CR_HSEON (1 << 16)
19 #define RCC_CR_HSERDY (1 << 17)
20 #define RCC_CR_HSEBYP (1 << 18)
21 #define RCC_CR_CSSON (1 << 19)
22 #define RCC_CR_PLLON (1 << 24)
23 #define RCC_CR_PLLRDY (1 << 25)
25 #define RCC_PLLCFGR_PLLM_MASK 0x3F
26 #define RCC_PLLCFGR_PLLN_MASK 0x7FC0
27 #define RCC_PLLCFGR_PLLP_MASK 0x30000
28 #define RCC_PLLCFGR_PLLQ_MASK 0xF000000
29 #define RCC_PLLCFGR_PLLSRC (1 << 22)
30 #define RCC_PLLCFGR_PLLN_SHIFT 6
31 #define RCC_PLLCFGR_PLLP_SHIFT 16
32 #define RCC_PLLCFGR_PLLQ_SHIFT 24
34 #define RCC_CFGR_AHB_PSC_MASK 0xF0
35 #define RCC_CFGR_APB1_PSC_MASK 0x1C00
36 #define RCC_CFGR_APB2_PSC_MASK 0xE000
37 #define RCC_CFGR_SW0 (1 << 0)
38 #define RCC_CFGR_SW1 (1 << 1)
39 #define RCC_CFGR_SW_MASK 0x3
40 #define RCC_CFGR_SW_HSI 0
41 #define RCC_CFGR_SW_HSE RCC_CFGR_SW0
42 #define RCC_CFGR_SW_PLL RCC_CFGR_SW1
43 #define RCC_CFGR_SWS0 (1 << 2)
44 #define RCC_CFGR_SWS1 (1 << 3)
45 #define RCC_CFGR_SWS_MASK 0xC
46 #define RCC_CFGR_SWS_HSI 0
47 #define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
48 #define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
49 #define RCC_CFGR_HPRE_SHIFT 4
50 #define RCC_CFGR_PPRE1_SHIFT 10
51 #define RCC_CFGR_PPRE2_SHIFT 13
53 #define RCC_APB1ENR_PWREN (1 << 28)
56 * RCC USART specific definitions
58 #define RCC_ENR_USART1EN (1 << 4)
59 #define RCC_ENR_USART2EN (1 << 17)
60 #define RCC_ENR_USART3EN (1 << 18)
61 #define RCC_ENR_USART6EN (1 << 5)
63 #define PWR_CR_VOS0 (1 << 14)
64 #define PWR_CR_VOS1 (1 << 15)
65 #define PWR_CR_VOS_MASK 0xC000
66 #define PWR_CR_VOS_SCALE_MODE_1 (PWR_CR_VOS0 | PWR_CR_VOS1)
67 #define PWR_CR_VOS_SCALE_MODE_2 (PWR_CR_VOS1)
68 #define PWR_CR_VOS_SCALE_MODE_3 (PWR_CR_VOS0)
71 * RCC GPIO specific definitions
73 #define RCC_ENR_GPIO_A_EN (1 << 0)
74 #define RCC_ENR_GPIO_B_EN (1 << 1)
75 #define RCC_ENR_GPIO_C_EN (1 << 2)
76 #define RCC_ENR_GPIO_D_EN (1 << 3)
77 #define RCC_ENR_GPIO_E_EN (1 << 4)
78 #define RCC_ENR_GPIO_F_EN (1 << 5)
79 #define RCC_ENR_GPIO_G_EN (1 << 6)
80 #define RCC_ENR_GPIO_H_EN (1 << 7)
81 #define RCC_ENR_GPIO_I_EN (1 << 8)
82 #define RCC_ENR_GPIO_J_EN (1 << 9)
83 #define RCC_ENR_GPIO_K_EN (1 << 10)
85 #if !defined(CONFIG_STM32_HSE_HZ)
86 #error "CONFIG_STM32_HSE_HZ not defined!"
88 #if (CONFIG_STM32_HSE_HZ == 8000000)
89 #if (CONFIG_SYS_CLK_FREQ == 180000000)
91 struct pll_psc sys_pll_psc
= {
97 .apb1_psc
= APB_PSC_4
,
101 /* default 168 MHz */
102 struct pll_psc sys_pll_psc
= {
107 .ahb_psc
= AHB_PSC_1
,
108 .apb1_psc
= APB_PSC_4
,
109 .apb2_psc
= APB_PSC_2
113 #error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
117 int configure_clocks(void)
119 /* Reset RCC configuration */
120 setbits_le32(&STM32_RCC
->cr
, RCC_CR_HSION
);
121 writel(0, &STM32_RCC
->cfgr
); /* Reset CFGR */
122 clrbits_le32(&STM32_RCC
->cr
, (RCC_CR_HSEON
| RCC_CR_CSSON
124 writel(0x24003010, &STM32_RCC
->pllcfgr
); /* Reset value from RM */
125 clrbits_le32(&STM32_RCC
->cr
, RCC_CR_HSEBYP
);
126 writel(0, &STM32_RCC
->cir
); /* Disable all interrupts */
128 /* Configure for HSE+PLL operation */
129 setbits_le32(&STM32_RCC
->cr
, RCC_CR_HSEON
);
130 while (!(readl(&STM32_RCC
->cr
) & RCC_CR_HSERDY
))
133 /* Enable high performance mode, System frequency up to 180 MHz */
134 setbits_le32(&STM32_RCC
->apb1enr
, RCC_APB1ENR_PWREN
);
135 writel(PWR_CR_VOS_SCALE_MODE_1
, &STM32_PWR
->cr
);
137 setbits_le32(&STM32_RCC
->cfgr
, ((
138 sys_pll_psc
.ahb_psc
<< RCC_CFGR_HPRE_SHIFT
)
139 | (sys_pll_psc
.apb1_psc
<< RCC_CFGR_PPRE1_SHIFT
)
140 | (sys_pll_psc
.apb2_psc
<< RCC_CFGR_PPRE2_SHIFT
)));
142 writel(sys_pll_psc
.pll_m
143 | (sys_pll_psc
.pll_n
<< RCC_PLLCFGR_PLLN_SHIFT
)
144 | (((sys_pll_psc
.pll_p
>> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT
)
145 | (sys_pll_psc
.pll_q
<< RCC_PLLCFGR_PLLQ_SHIFT
),
146 &STM32_RCC
->pllcfgr
);
147 setbits_le32(&STM32_RCC
->pllcfgr
, RCC_PLLCFGR_PLLSRC
);
149 setbits_le32(&STM32_RCC
->cr
, RCC_CR_PLLON
);
151 while (!(readl(&STM32_RCC
->cr
) & RCC_CR_PLLRDY
))
154 stm32_flash_latency_cfg(5);
155 clrbits_le32(&STM32_RCC
->cfgr
, (RCC_CFGR_SW0
| RCC_CFGR_SW1
));
156 setbits_le32(&STM32_RCC
->cfgr
, RCC_CFGR_SW_PLL
);
158 while ((readl(&STM32_RCC
->cfgr
) & RCC_CFGR_SWS_MASK
) !=
165 unsigned long clock_get(enum clock clck
)
169 /* Prescaler table lookups for clock computation */
170 u8 ahb_psc_table
[16] = {
171 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
173 u8 apb_psc_table
[8] = {
174 0, 0, 0, 0, 1, 2, 3, 4
177 if ((readl(&STM32_RCC
->cfgr
) & RCC_CFGR_SWS_MASK
) ==
179 u16 pllm
, plln
, pllp
;
180 pllm
= (readl(&STM32_RCC
->pllcfgr
) & RCC_PLLCFGR_PLLM_MASK
);
181 plln
= ((readl(&STM32_RCC
->pllcfgr
) & RCC_PLLCFGR_PLLN_MASK
)
182 >> RCC_PLLCFGR_PLLN_SHIFT
);
183 pllp
= ((((readl(&STM32_RCC
->pllcfgr
) & RCC_PLLCFGR_PLLP_MASK
)
184 >> RCC_PLLCFGR_PLLP_SHIFT
) + 1) << 1);
185 sysclk
= ((CONFIG_STM32_HSE_HZ
/ pllm
) * plln
) / pllp
;
193 shift
= ahb_psc_table
[(
194 (readl(&STM32_RCC
->cfgr
) & RCC_CFGR_AHB_PSC_MASK
)
195 >> RCC_CFGR_HPRE_SHIFT
)];
196 return sysclk
>>= shift
;
199 shift
= apb_psc_table
[(
200 (readl(&STM32_RCC
->cfgr
) & RCC_CFGR_APB1_PSC_MASK
)
201 >> RCC_CFGR_PPRE1_SHIFT
)];
202 return sysclk
>>= shift
;
205 shift
= apb_psc_table
[(
206 (readl(&STM32_RCC
->cfgr
) & RCC_CFGR_APB2_PSC_MASK
)
207 >> RCC_CFGR_PPRE2_SHIFT
)];
208 return sysclk
>>= shift
;
216 void clock_setup(int peripheral
)
218 switch (peripheral
) {
219 case USART1_CLOCK_CFG
:
220 setbits_le32(&STM32_RCC
->apb2enr
, RCC_ENR_USART1EN
);
222 case GPIO_A_CLOCK_CFG
:
223 setbits_le32(&STM32_RCC
->ahb1enr
, RCC_ENR_GPIO_A_EN
);
225 case GPIO_B_CLOCK_CFG
:
226 setbits_le32(&STM32_RCC
->ahb1enr
, RCC_ENR_GPIO_B_EN
);
228 case GPIO_C_CLOCK_CFG
:
229 setbits_le32(&STM32_RCC
->ahb1enr
, RCC_ENR_GPIO_C_EN
);
231 case GPIO_D_CLOCK_CFG
:
232 setbits_le32(&STM32_RCC
->ahb1enr
, RCC_ENR_GPIO_D_EN
);
234 case GPIO_E_CLOCK_CFG
:
235 setbits_le32(&STM32_RCC
->ahb1enr
, RCC_ENR_GPIO_E_EN
);
237 case GPIO_F_CLOCK_CFG
:
238 setbits_le32(&STM32_RCC
->ahb1enr
, RCC_ENR_GPIO_F_EN
);
240 case GPIO_G_CLOCK_CFG
:
241 setbits_le32(&STM32_RCC
->ahb1enr
, RCC_ENR_GPIO_G_EN
);
243 case GPIO_H_CLOCK_CFG
:
244 setbits_le32(&STM32_RCC
->ahb1enr
, RCC_ENR_GPIO_H_EN
);
246 case GPIO_I_CLOCK_CFG
:
247 setbits_le32(&STM32_RCC
->ahb1enr
, RCC_ENR_GPIO_I_EN
);
249 case GPIO_J_CLOCK_CFG
:
250 setbits_le32(&STM32_RCC
->ahb1enr
, RCC_ENR_GPIO_J_EN
);
252 case GPIO_K_CLOCK_CFG
:
253 setbits_le32(&STM32_RCC
->ahb1enr
, RCC_ENR_GPIO_K_EN
);