arch/arm/mach-sunxi/Kconfig

   1 if ARCH_SUNXI
   2
   3 config SPL_LDSCRIPT
   4         default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
   5
   6 config IDENT_STRING
   7         default " Allwinner Technology"
   8
   9 config SUNXI_HIGH_SRAM
  10         bool
  11         default n
  12         ---help---
  13         Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
  14         with the first SRAM region being located at address 0.
  15         Some newer SoCs map the boot ROM at address 0 instead and move the
  16         SRAM to 64KB, just behind the mask ROM.
  17         Chips using the latter setup are supposed to select this option to
  18         adjust the addresses accordingly.
  19
  20 # Note only one of these may be selected at a time! But hidden choices are
  21 # not supported by Kconfig
  22 config SUNXI_GEN_SUN4I
  23         bool
  24         ---help---
  25         Select this for sunxi SoCs which have resets and clocks set up
  26         as the original A10 (mach-sun4i).
  27
  28 config SUNXI_GEN_SUN6I
  29         bool
  30         ---help---
  31         Select this for sunxi SoCs which have sun6i like periphery, like
  32         separate ahb reset control registers, custom pmic bus, new style
  33         watchdog, etc.
  34
  35 config SUNXI_DRAM_DW
  36         bool
  37         ---help---
  38         Select this for sunxi SoCs which uses a DRAM controller like the
  39         DesignWare controller used in H3, mainly SoCs after H3, which do
  40         not have official open-source DRAM initialization code, but can
  41         use modified H3 DRAM initialization code.
  42
  43 if SUNXI_DRAM_DW
  44 config SUNXI_DRAM_DW_16BIT
  45         bool
  46         ---help---
  47         Select this for sunxi SoCs with DesignWare DRAM controller and
  48         have only 16-bit memory buswidth.
  49
  50 config SUNXI_DRAM_DW_32BIT
  51         bool
  52         ---help---
  53         Select this for sunxi SoCs with DesignWare DRAM controller with
  54         32-bit memory buswidth.
  55 endif
  56
  57 config MACH_SUNXI_H3_H5
  58         bool
  59         select DM_I2C
  60         select SUNXI_DE2
  61         select SUNXI_DRAM_DW
  62         select SUNXI_DRAM_DW_32BIT
  63         select SUNXI_GEN_SUN6I
  64         select SUPPORT_SPL
  65
  66 choice
  67         prompt "Sunxi SoC Variant"
  68         optional
  69
  70 config MACH_SUN4I
  71         bool "sun4i (Allwinner A10)"
  72         select CPU_V7
  73         select ARM_CORTEX_CPU_IS_UP
  74         select SUNXI_GEN_SUN4I
  75         select SUPPORT_SPL
  76
  77 config MACH_SUN5I
  78         bool "sun5i (Allwinner A13)"
  79         select CPU_V7
  80         select ARM_CORTEX_CPU_IS_UP
  81         select SUNXI_GEN_SUN4I
  82         select SUPPORT_SPL
  83
  84 config MACH_SUN6I
  85         bool "sun6i (Allwinner A31)"
  86         select CPU_V7
  87         select CPU_V7_HAS_NONSEC
  88         select CPU_V7_HAS_VIRT
  89         select ARCH_SUPPORT_PSCI
  90         select SUNXI_GEN_SUN6I
  91         select SUPPORT_SPL
  92         select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
  93
  94 config MACH_SUN7I
  95         bool "sun7i (Allwinner A20)"
  96         select CPU_V7
  97         select CPU_V7_HAS_NONSEC
  98         select CPU_V7_HAS_VIRT
  99         select ARCH_SUPPORT_PSCI
 100         select SUNXI_GEN_SUN4I
 101         select SUPPORT_SPL
 102         select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 103
 104 config MACH_SUN8I_A23
 105         bool "sun8i (Allwinner A23)"
 106         select CPU_V7
 107         select CPU_V7_HAS_NONSEC
 108         select CPU_V7_HAS_VIRT
 109         select ARCH_SUPPORT_PSCI
 110         select SUNXI_GEN_SUN6I
 111         select SUPPORT_SPL
 112         select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 113
 114 config MACH_SUN8I_A33
 115         bool "sun8i (Allwinner A33)"
 116         select CPU_V7
 117         select CPU_V7_HAS_NONSEC
 118         select CPU_V7_HAS_VIRT
 119         select ARCH_SUPPORT_PSCI
 120         select SUNXI_GEN_SUN6I
 121         select SUPPORT_SPL
 122         select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 123
 124 config MACH_SUN8I_A83T
 125         bool "sun8i (Allwinner A83T)"
 126         select CPU_V7
 127         select SUNXI_GEN_SUN6I
 128         select MMC_SUNXI_HAS_NEW_MODE
 129         select SUPPORT_SPL
 130
 131 config MACH_SUN8I_H3
 132         bool "sun8i (Allwinner H3)"
 133         select CPU_V7
 134         select CPU_V7_HAS_NONSEC
 135         select CPU_V7_HAS_VIRT
 136         select ARCH_SUPPORT_PSCI
 137         select MACH_SUNXI_H3_H5
 138         select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 139
 140 config MACH_SUN8I_R40
 141         bool "sun8i (Allwinner R40)"
 142         select CPU_V7
 143         select CPU_V7_HAS_NONSEC
 144         select CPU_V7_HAS_VIRT
 145         select ARCH_SUPPORT_PSCI
 146         select SUNXI_GEN_SUN6I
 147         select SUPPORT_SPL
 148         select SUNXI_DRAM_DW
 149         select SUNXI_DRAM_DW_32BIT
 150
 151 config MACH_SUN8I_V3S
 152         bool "sun8i (Allwinner V3s)"
 153         select CPU_V7
 154         select CPU_V7_HAS_NONSEC
 155         select CPU_V7_HAS_VIRT
 156         select ARCH_SUPPORT_PSCI
 157         select SUNXI_GEN_SUN6I
 158         select SUNXI_DRAM_DW
 159         select SUNXI_DRAM_DW_16BIT
 160         select SUPPORT_SPL
 161         select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
 162
 163 config MACH_SUN9I
 164         bool "sun9i (Allwinner A80)"
 165         select CPU_V7
 166         select SUNXI_HIGH_SRAM
 167         select SUNXI_GEN_SUN6I
 168         select SUPPORT_SPL
 169
 170 config MACH_SUN50I
 171         bool "sun50i (Allwinner A64)"
 172         select ARM64
 173         select DM_I2C
 174         select SUNXI_DE2
 175         select SUNXI_GEN_SUN6I
 176         select SUNXI_HIGH_SRAM
 177         select SUPPORT_SPL
 178         select SUNXI_DRAM_DW
 179         select SUNXI_DRAM_DW_32BIT
 180         select FIT
 181         select SPL_LOAD_FIT
 182
 183 config MACH_SUN50I_H5
 184         bool "sun50i (Allwinner H5)"
 185         select ARM64
 186         select MACH_SUNXI_H3_H5
 187         select SUNXI_HIGH_SRAM
 188         select FIT
 189         select SPL_LOAD_FIT
 190
 191 endchoice
 192
 193 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
 194 config MACH_SUN8I
 195         bool
 196         default y if MACH_SUN8I_A23
 197         default y if MACH_SUN8I_A33
 198         default y if MACH_SUN8I_A83T
 199         default y if MACH_SUNXI_H3_H5
 200         default y if MACH_SUN8I_R40
 201         default y if MACH_SUN8I_V3S
 202
 203 config RESERVE_ALLWINNER_BOOT0_HEADER
 204         bool "reserve space for Allwinner boot0 header"
 205         select ENABLE_ARM_SOC_BOOT0_HOOK
 206         ---help---
 207         Prepend a 1536 byte (empty) header to the U-Boot image file, to be
 208         filled with magic values post build. The Allwinner provided boot0
 209         blob relies on this information to load and execute U-Boot.
 210         Only needed on 64-bit Allwinner boards so far when using boot0.
 211
 212 config ARM_BOOT_HOOK_RMR
 213         bool
 214         depends on ARM64
 215         default y
 216         select ENABLE_ARM_SOC_BOOT0_HOOK
 217         ---help---
 218         Insert some ARM32 code at the very beginning of the U-Boot binary
 219         which uses an RMR register write to bring the core into AArch64 mode.
 220         The very first instruction acts as a switch, since it's carefully
 221         chosen to be a NOP in one mode and a branch in the other, so the
 222         code would only be executed if not already in AArch64.
 223         This allows both the SPL and the U-Boot proper to be entered in
 224         either mode and switch to AArch64 if needed.
 225
 226 if SUNXI_DRAM_DW
 227 config SUNXI_DRAM_DDR3
 228         bool
 229
 230 config SUNXI_DRAM_DDR2
 231         bool
 232
 233 config SUNXI_DRAM_LPDDR3
 234         bool
 235
 236 choice
 237         prompt "DRAM Type and Timing"
 238         default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
 239         default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
 240
 241 config SUNXI_DRAM_DDR3_1333
 242         bool "DDR3 1333"
 243         select SUNXI_DRAM_DDR3
 244         depends on !MACH_SUN8I_V3S
 245         ---help---
 246         This option is the original only supported memory type, which suits
 247         many H3/H5/A64 boards available now.
 248
 249 config SUNXI_DRAM_LPDDR3_STOCK
 250         bool "LPDDR3 with Allwinner stock configuration"
 251         select SUNXI_DRAM_LPDDR3
 252         ---help---
 253         This option is the LPDDR3 timing used by the stock boot0 by
 254         Allwinner.
 255
 256 config SUNXI_DRAM_DDR2_V3S
 257         bool "DDR2 found in V3s chip"
 258         select SUNXI_DRAM_DDR2
 259         depends on MACH_SUN8I_V3S
 260         ---help---
 261         This option is only for the DDR2 memory chip which is co-packaged in
 262         Allwinner V3s SoC.
 263
 264 endchoice
 265 endif
 266
 267 config DRAM_TYPE
 268         int "sunxi dram type"
 269         depends on MACH_SUN8I_A83T
 270         default 3
 271         ---help---
 272         Set the dram type, 3: DDR3, 7: LPDDR3
 273
 274 config DRAM_CLK
 275         int "sunxi dram clock speed"
 276         default 792 if MACH_SUN9I
 277         default 648 if MACH_SUN8I_R40
 278         default 312 if MACH_SUN6I || MACH_SUN8I
 279         default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
 280                        MACH_SUN8I_V3S
 281         default 672 if MACH_SUN50I
 282         ---help---
 283         Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
 284         must be a multiple of 24. For the sun9i (A80), the tested values
 285         (for DDR3-1600) are 312 to 792.
 286
 287 if MACH_SUN5I || MACH_SUN7I
 288 config DRAM_MBUS_CLK
 289         int "sunxi mbus clock speed"
 290         default 300
 291         ---help---
 292         Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
 293
 294 endif
 295
 296 config DRAM_ZQ
 297         int "sunxi dram zq value"
 298         default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
 299         default 127 if MACH_SUN7I
 300         default 14779 if MACH_SUN8I_V3S
 301         default 3881979 if MACH_SUN8I_R40
 302         default 4145117 if MACH_SUN9I
 303         default 3881915 if MACH_SUN50I
 304         ---help---
 305         Set the dram zq value.
 306
 307 config DRAM_ODT_EN
 308         bool "sunxi dram odt enable"
 309         default n if !MACH_SUN8I_A23
 310         default y if MACH_SUN8I_A23
 311         default y if MACH_SUN8I_R40
 312         default y if MACH_SUN50I
 313         ---help---
 314         Select this to enable dram odt (on die termination).
 315
 316 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
 317 config DRAM_EMR1
 318         int "sunxi dram emr1 value"
 319         default 0 if MACH_SUN4I
 320         default 4 if MACH_SUN5I || MACH_SUN7I
 321         ---help---
 322         Set the dram controller emr1 value.
 323
 324 config DRAM_TPR3
 325         hex "sunxi dram tpr3 value"
 326         default 0
 327         ---help---
 328         Set the dram controller tpr3 parameter. This parameter configures
 329         the delay on the command lane and also phase shifts, which are
 330         applied for sampling incoming read data. The default value 0
 331         means that no phase/delay adjustments are necessary. Properly
 332         configuring this parameter increases reliability at high DRAM
 333         clock speeds.
 334
 335 config DRAM_DQS_GATING_DELAY
 336         hex "sunxi dram dqs_gating_delay value"
 337         default 0
 338         ---help---
 339         Set the dram controller dqs_gating_delay parmeter. Each byte
 340         encodes the DQS gating delay for each byte lane. The delay
 341         granularity is 1/4 cycle. For example, the value 0x05060606
 342         means that the delay is 5 quarter-cycles for one lane (1.25
 343         cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
 344         The default value 0 means autodetection. The results of hardware
 345         autodetection are not very reliable and depend on the chip
 346         temperature (sometimes producing different results on cold start
 347         and warm reboot). But the accuracy of hardware autodetection
 348         is usually good enough, unless running at really high DRAM
 349         clocks speeds (up to 600MHz). If unsure, keep as 0.
 350
 351 choice
 352         prompt "sunxi dram timings"
 353         default DRAM_TIMINGS_VENDOR_MAGIC
 354         ---help---
 355         Select the timings of the DDR3 chips.
 356
 357 config DRAM_TIMINGS_VENDOR_MAGIC
 358         bool "Magic vendor timings from Android"
 359         ---help---
 360         The same DRAM timings as in the Allwinner boot0 bootloader.
 361
 362 config DRAM_TIMINGS_DDR3_1066F_1333H
 363         bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
 364         ---help---
 365         Use the timings of the standard JEDEC DDR3-1066F speed bin for
 366         DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
 367         for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
 368         used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
 369         or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
 370         that down binning to DDR3-1066F is supported (because DDR3-1066F
 371         uses a bit faster timings than DDR3-1333H).
 372
 373 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
 374         bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
 375         ---help---
 376         Use the timings of the slowest possible JEDEC speed bin for the
 377         selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
 378         DDR3-800E, DDR3-1066G or DDR3-1333J.
 379
 380 endchoice
 381
 382 endif
 383
 384 if MACH_SUN8I_A23
 385 config DRAM_ODT_CORRECTION
 386         int "sunxi dram odt correction value"
 387         default 0
 388         ---help---
 389         Set the dram odt correction value (range -255 - 255). In allwinner
 390         fex files, this option is found in bits 8-15 of the u32 odt_en variable
 391         in the [dram] section. When bit 31 of the odt_en variable is set
 392         then the correction is negative. Usually the value for this is 0.
 393 endif
 394
 395 config SYS_CLK_FREQ
 396         default 1008000000 if MACH_SUN4I
 397         default 1008000000 if MACH_SUN5I
 398         default 1008000000 if MACH_SUN6I
 399         default 912000000 if MACH_SUN7I
 400         default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
 401         default 1008000000 if MACH_SUN8I
 402         default 1008000000 if MACH_SUN9I
 403
 404 config SYS_CONFIG_NAME
 405         default "sun4i" if MACH_SUN4I
 406         default "sun5i" if MACH_SUN5I
 407         default "sun6i" if MACH_SUN6I
 408         default "sun7i" if MACH_SUN7I
 409         default "sun8i" if MACH_SUN8I
 410         default "sun9i" if MACH_SUN9I
 411         default "sun50i" if MACH_SUN50I
 412
 413 config SYS_BOARD
 414         default "sunxi"
 415
 416 config SYS_SOC
 417         default "sunxi"
 418
 419 config UART0_PORT_F
 420         bool "UART0 on MicroSD breakout board"
 421         default n
 422         ---help---
 423         Repurpose the SD card slot for getting access to the UART0 serial
 424         console. Primarily useful only for low level u-boot debugging on
 425         tablets, where normal UART0 is difficult to access and requires
 426         device disassembly and/or soldering. As the SD card can't be used
 427         at the same time, the system can be only booted in the FEL mode.
 428         Only enable this if you really know what you are doing.
 429
 430 config OLD_SUNXI_KERNEL_COMPAT
 431         bool "Enable workarounds for booting old kernels"
 432         default n
 433         ---help---
 434         Set this to enable various workarounds for old kernels, this results in
 435         sub-optimal settings for newer kernels, only enable if needed.
 436
 437 config MACPWR
 438         string "MAC power pin"
 439         default ""
 440         help
 441           Set the pin used to power the MAC. This takes a string in the format
 442           understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 443
 444 config MMC0_CD_PIN
 445         string "Card detect pin for mmc0"
 446         default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
 447         default ""
 448         ---help---
 449         Set the card detect pin for mmc0, leave empty to not use cd. This
 450         takes a string in the format understood by sunxi_name_to_gpio, e.g.
 451         PH1 for pin 1 of port H.
 452
 453 config MMC1_CD_PIN
 454         string "Card detect pin for mmc1"
 455         default ""
 456         ---help---
 457         See MMC0_CD_PIN help text.
 458
 459 config MMC2_CD_PIN
 460         string "Card detect pin for mmc2"
 461         default ""
 462         ---help---
 463         See MMC0_CD_PIN help text.
 464
 465 config MMC3_CD_PIN
 466         string "Card detect pin for mmc3"
 467         default ""
 468         ---help---
 469         See MMC0_CD_PIN help text.
 470
 471 config MMC1_PINS
 472         string "Pins for mmc1"
 473         default ""
 474         ---help---
 475         Set the pins used for mmc1, when applicable. This takes a string in the
 476         format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
 477
 478 config MMC2_PINS
 479         string "Pins for mmc2"
 480         default ""
 481         ---help---
 482         See MMC1_PINS help text.
 483
 484 config MMC3_PINS
 485         string "Pins for mmc3"
 486         default ""
 487         ---help---
 488         See MMC1_PINS help text.
 489
 490 config MMC_SUNXI_SLOT_EXTRA
 491         int "mmc extra slot number"
 492         default -1
 493         ---help---
 494         sunxi builds always enable mmc0, some boards also have a second sdcard
 495         slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
 496         support for this.
 497
 498 config INITIAL_USB_SCAN_DELAY
 499         int "delay initial usb scan by x ms to allow builtin devices to init"
 500         default 0
 501         ---help---
 502         Some boards have on board usb devices which need longer than the
 503         USB spec's 1 second to connect from board powerup. Set this config
 504         option to a non 0 value to add an extra delay before the first usb
 505         bus scan.
 506
 507 config USB0_VBUS_PIN
 508         string "Vbus enable pin for usb0 (otg)"
 509         default ""
 510         ---help---
 511         Set the Vbus enable pin for usb0 (otg). This takes a string in the
 512         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 513
 514 config USB0_VBUS_DET
 515         string "Vbus detect pin for usb0 (otg)"
 516         default ""
 517         ---help---
 518         Set the Vbus detect pin for usb0 (otg). This takes a string in the
 519         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 520
 521 config USB0_ID_DET
 522         string "ID detect pin for usb0 (otg)"
 523         default ""
 524         ---help---
 525         Set the ID detect pin for usb0 (otg). This takes a string in the
 526         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 527
 528 config USB1_VBUS_PIN
 529         string "Vbus enable pin for usb1 (ehci0)"
 530         default "PH6" if MACH_SUN4I || MACH_SUN7I
 531         default "PH27" if MACH_SUN6I
 532         ---help---
 533         Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
 534         a string in the format understood by sunxi_name_to_gpio, e.g.
 535         PH1 for pin 1 of port H.
 536
 537 config USB2_VBUS_PIN
 538         string "Vbus enable pin for usb2 (ehci1)"
 539         default "PH3" if MACH_SUN4I || MACH_SUN7I
 540         default "PH24" if MACH_SUN6I
 541         ---help---
 542         See USB1_VBUS_PIN help text.
 543
 544 config USB3_VBUS_PIN
 545         string "Vbus enable pin for usb3 (ehci2)"
 546         default ""
 547         ---help---
 548         See USB1_VBUS_PIN help text.
 549
 550 config I2C0_ENABLE
 551         bool "Enable I2C/TWI controller 0"
 552         default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
 553         default n if MACH_SUN6I || MACH_SUN8I
 554         select CMD_I2C
 555         ---help---
 556         This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
 557         its clock and setting up the bus. This is especially useful on devices
 558         with slaves connected to the bus or with pins exposed through e.g. an
 559         expansion port/header.
 560
 561 config I2C1_ENABLE
 562         bool "Enable I2C/TWI controller 1"
 563         default n
 564         select CMD_I2C
 565         ---help---
 566         See I2C0_ENABLE help text.
 567
 568 config I2C2_ENABLE
 569         bool "Enable I2C/TWI controller 2"
 570         default n
 571         select CMD_I2C
 572         ---help---
 573         See I2C0_ENABLE help text.
 574
 575 if MACH_SUN6I || MACH_SUN7I
 576 config I2C3_ENABLE
 577         bool "Enable I2C/TWI controller 3"
 578         default n
 579         select CMD_I2C
 580         ---help---
 581         See I2C0_ENABLE help text.
 582 endif
 583
 584 if SUNXI_GEN_SUN6I
 585 config R_I2C_ENABLE
 586         bool "Enable the PRCM I2C/TWI controller"
 587         # This is used for the pmic on H3
 588         default y if SY8106A_POWER
 589         select CMD_I2C
 590         ---help---
 591         Set this to y to enable the I2C controller which is part of the PRCM.
 592 endif
 593
 594 if MACH_SUN7I
 595 config I2C4_ENABLE
 596         bool "Enable I2C/TWI controller 4"
 597         default n
 598         select CMD_I2C
 599         ---help---
 600         See I2C0_ENABLE help text.
 601 endif
 602
 603 config AXP_GPIO
 604         bool "Enable support for gpio-s on axp PMICs"
 605         default n
 606         ---help---
 607         Say Y here to enable support for the gpio pins of the axp PMIC ICs.
 608
 609 config VIDEO_SUNXI
 610         bool "Enable graphical uboot console on HDMI, LCD or VGA"
 611         depends on !MACH_SUN8I_A83T
 612         depends on !MACH_SUNXI_H3_H5
 613         depends on !MACH_SUN8I_R40
 614         depends on !MACH_SUN8I_V3S
 615         depends on !MACH_SUN9I
 616         depends on !MACH_SUN50I
 617         select VIDEO
 618         imply VIDEO_DT_SIMPLEFB
 619         default y
 620         ---help---
 621         Say Y here to add support for using a cfb console on the HDMI, LCD
 622         or VGA output found on most sunxi devices. See doc/README.video for
 623         info on how to select the video output and mode.
 624
 625 config VIDEO_HDMI
 626         bool "HDMI output support"
 627         depends on VIDEO_SUNXI && !MACH_SUN8I
 628         default y
 629         ---help---
 630         Say Y here to add support for outputting video over HDMI.
 631
 632 config VIDEO_VGA
 633         bool "VGA output support"
 634         depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
 635         default n
 636         ---help---
 637         Say Y here to add support for outputting video over VGA.
 638
 639 config VIDEO_VGA_VIA_LCD
 640         bool "VGA via LCD controller support"
 641         depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
 642         default n
 643         ---help---
 644         Say Y here to add support for external DACs connected to the parallel
 645         LCD interface driving a VGA connector, such as found on the
 646         Olimex A13 boards.
 647
 648 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
 649         bool "Force sync active high for VGA via LCD controller support"
 650         depends on VIDEO_VGA_VIA_LCD
 651         default n
 652         ---help---
 653         Say Y here if you've a board which uses opendrain drivers for the vga
 654         hsync and vsync signals. Opendrain drivers cannot generate steep enough
 655         positive edges for a stable video output, so on boards with opendrain
 656         drivers the sync signals must always be active high.
 657
 658 config VIDEO_VGA_EXTERNAL_DAC_EN
 659         string "LCD panel power enable pin"
 660         depends on VIDEO_VGA_VIA_LCD
 661         default ""
 662         ---help---
 663         Set the enable pin for the external VGA DAC. This takes a string in the
 664         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 665
 666 config VIDEO_COMPOSITE
 667         bool "Composite video output support"
 668         depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
 669         default n
 670         ---help---
 671         Say Y here to add support for outputting composite video.
 672
 673 config VIDEO_LCD_MODE
 674         string "LCD panel timing details"
 675         depends on VIDEO_SUNXI
 676         default ""
 677         ---help---
 678         LCD panel timing details string, leave empty if there is no LCD panel.
 679         This is in drivers/video/videomodes.c: video_get_params() format, e.g.
 680         x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
 681         Also see: http://linux-sunxi.org/LCD
 682
 683 config VIDEO_LCD_DCLK_PHASE
 684         int "LCD panel display clock phase"
 685         depends on VIDEO_SUNXI || DM_VIDEO
 686         default 1
 687         ---help---
 688         Select LCD panel display clock phase shift, range 0-3.
 689
 690 config VIDEO_LCD_POWER
 691         string "LCD panel power enable pin"
 692         depends on VIDEO_SUNXI
 693         default ""
 694         ---help---
 695         Set the power enable pin for the LCD panel. This takes a string in the
 696         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 697
 698 config VIDEO_LCD_RESET
 699         string "LCD panel reset pin"
 700         depends on VIDEO_SUNXI
 701         default ""
 702         ---help---
 703         Set the reset pin for the LCD panel. This takes a string in the format
 704         understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 705
 706 config VIDEO_LCD_BL_EN
 707         string "LCD panel backlight enable pin"
 708         depends on VIDEO_SUNXI
 709         default ""
 710         ---help---
 711         Set the backlight enable pin for the LCD panel. This takes a string in the
 712         the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
 713         port H.
 714
 715 config VIDEO_LCD_BL_PWM
 716         string "LCD panel backlight pwm pin"
 717         depends on VIDEO_SUNXI
 718         default ""
 719         ---help---
 720         Set the backlight pwm pin for the LCD panel. This takes a string in the
 721         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 722
 723 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
 724         bool "LCD panel backlight pwm is inverted"
 725         depends on VIDEO_SUNXI
 726         default y
 727         ---help---
 728         Set this if the backlight pwm output is active low.
 729
 730 config VIDEO_LCD_PANEL_I2C
 731         bool "LCD panel needs to be configured via i2c"
 732         depends on VIDEO_SUNXI
 733         default n
 734         select CMD_I2C
 735         ---help---
 736         Say y here if the LCD panel needs to be configured via i2c. This
 737         will add a bitbang i2c controller using gpios to talk to the LCD.
 738
 739 config VIDEO_LCD_PANEL_I2C_SDA
 740         string "LCD panel i2c interface SDA pin"
 741         depends on VIDEO_LCD_PANEL_I2C
 742         default "PG12"
 743         ---help---
 744         Set the SDA pin for the LCD i2c interface. This takes a string in the
 745         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 746
 747 config VIDEO_LCD_PANEL_I2C_SCL
 748         string "LCD panel i2c interface SCL pin"
 749         depends on VIDEO_LCD_PANEL_I2C
 750         default "PG10"
 751         ---help---
 752         Set the SCL pin for the LCD i2c interface. This takes a string in the
 753         format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
 754
 755
 756 # Note only one of these may be selected at a time! But hidden choices are
 757 # not supported by Kconfig
 758 config VIDEO_LCD_IF_PARALLEL
 759         bool
 760
 761 config VIDEO_LCD_IF_LVDS
 762         bool
 763
 764 config SUNXI_DE2
 765         bool
 766         default n
 767
 768 config VIDEO_DE2
 769         bool "Display Engine 2 video driver"
 770         depends on SUNXI_DE2
 771         select DM_VIDEO
 772         select DISPLAY
 773         imply VIDEO_DT_SIMPLEFB
 774         default y
 775         ---help---
 776         Say y here if you want to build DE2 video driver which is present on
 777         newer SoCs. Currently only HDMI output is supported.
 778
 779
 780 choice
 781         prompt "LCD panel support"
 782         depends on VIDEO_SUNXI
 783         ---help---
 784         Select which type of LCD panel to support.
 785
 786 config VIDEO_LCD_PANEL_PARALLEL
 787         bool "Generic parallel interface LCD panel"
 788         select VIDEO_LCD_IF_PARALLEL
 789
 790 config VIDEO_LCD_PANEL_LVDS
 791         bool "Generic lvds interface LCD panel"
 792         select VIDEO_LCD_IF_LVDS
 793
 794 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
 795         bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
 796         select VIDEO_LCD_SSD2828
 797         select VIDEO_LCD_IF_PARALLEL
 798         ---help---
 799         7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
 800
 801 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
 802         bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
 803         select VIDEO_LCD_ANX9804
 804         select VIDEO_LCD_IF_PARALLEL
 805         select VIDEO_LCD_PANEL_I2C
 806         ---help---
 807         Select this for eDP LCD panels with 4 lanes running at 1.62G,
 808         connected via an ANX9804 bridge chip.
 809
 810 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
 811         bool "Hitachi tx18d42vm LCD panel"
 812         select VIDEO_LCD_HITACHI_TX18D42VM
 813         select VIDEO_LCD_IF_LVDS
 814         ---help---
 815         7.85" 1024x768 Hitachi tx18d42vm LCD panel support
 816
 817 config VIDEO_LCD_TL059WV5C0
 818         bool "tl059wv5c0 LCD panel"
 819         select VIDEO_LCD_PANEL_I2C
 820         select VIDEO_LCD_IF_PARALLEL
 821         ---help---
 822         6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
 823         Aigo M60/M608/M606 tablets.
 824
 825 endchoice
 826
 827 config SATAPWR
 828         string "SATA power pin"
 829         default ""
 830         help
 831           Set the pins used to power the SATA. This takes a string in the
 832           format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
 833           port H.
 834
 835 config GMAC_TX_DELAY
 836         int "GMAC Transmit Clock Delay Chain"
 837         default 0
 838         ---help---
 839         Set the GMAC Transmit Clock Delay Chain value.
 840
 841 config SPL_STACK_R_ADDR
 842         default 0x4fe00000 if MACH_SUN4I
 843         default 0x4fe00000 if MACH_SUN5I
 844         default 0x4fe00000 if MACH_SUN6I
 845         default 0x4fe00000 if MACH_SUN7I
 846         default 0x4fe00000 if MACH_SUN8I
 847         default 0x2fe00000 if MACH_SUN9I
 848         default 0x4fe00000 if MACH_SUN50I
 849
 850 endif