arch/arm/mach-sunxi/board.c

   1 /*
   2  * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
   3  *
   4  * (C) Copyright 2007-2011
   5  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   6  * Tom Cubie <tangliang@allwinnertech.com>
   7  *
   8  * Some init for sunxi platform.
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <mmc.h>
  15 #include <i2c.h>
  16 #include <serial.h>
  17 #ifdef CONFIG_SPL_BUILD
  18 #include <spl.h>
  19 #endif
  20 #include <asm/gpio.h>
  21 #include <asm/io.h>
  22 #include <asm/arch/clock.h>
  23 #include <asm/arch/gpio.h>
  24 #include <asm/arch/spl.h>
  25 #include <asm/arch/sys_proto.h>
  26 #include <asm/arch/timer.h>
  27 #include <asm/arch/tzpc.h>
  28 #include <asm/arch/mmc.h>
  29
  30 #include <linux/compiler.h>
  31
  32 struct fel_stash {
  33         uint32_t sp;
  34         uint32_t lr;
  35         uint32_t cpsr;
  36         uint32_t sctlr;
  37         uint32_t vbar;
  38         uint32_t cr;
  39 };
  40
  41 struct fel_stash fel_stash __attribute__((section(".data")));
  42
  43 #ifdef CONFIG_MACH_SUN50I
  44 #include <asm/armv8/mmu.h>
  45
  46 static struct mm_region sunxi_mem_map[] = {
  47         {
  48                 /* SRAM, MMIO regions */
  49                 .virt = 0x0UL,
  50                 .phys = 0x0UL,
  51                 .size = 0x40000000UL,
  52                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  53                          PTE_BLOCK_NON_SHARE
  54         }, {
  55                 /* RAM */
  56                 .virt = 0x40000000UL,
  57                 .phys = 0x40000000UL,
  58                 .size = 0x80000000UL,
  59                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  60                          PTE_BLOCK_INNER_SHARE
  61         }, {
  62                 /* List terminator */
  63                 0,
  64         }
  65 };
  66 struct mm_region *mem_map = sunxi_mem_map;
  67 #endif
  68
  69 static int gpio_init(void)
  70 {
  71 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
  72 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
  73         /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
  74         sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
  75         sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
  76 #endif
  77 #if defined(CONFIG_MACH_SUN8I)
  78         sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
  79         sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
  80 #else
  81         sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
  82         sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
  83 #endif
  84         sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
  85 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
  86         sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
  87         sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
  88         sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
  89 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
  90         sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
  91         sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
  92         sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
  93 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
  94         sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
  95         sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
  96         sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
  97 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
  98         sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
  99         sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
 100         sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
 101 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_H3)
 102         sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
 103         sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
 104         sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
 105 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
 106         sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
 107         sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
 108         sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
 109 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
 110         sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
 111         sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
 112         sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
 113 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
 114         sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
 115         sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
 116         sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
 117 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
 118         sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
 119         sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
 120         sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
 121 #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
 122         sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
 123         sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
 124         sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
 125 #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
 126         sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
 127         sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
 128         sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
 129 #else
 130 #error Unsupported console port number. Please fix pin mux settings in board.c
 131 #endif
 132
 133         return 0;
 134 }
 135
 136 #ifdef CONFIG_SPL_BUILD
 137 static int spl_board_load_image(struct spl_image_info *spl_image,
 138                                 struct spl_boot_device *bootdev)
 139 {
 140         debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
 141         return_to_fel(fel_stash.sp, fel_stash.lr);
 142
 143         return 0;
 144 }
 145 SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
 146 #endif
 147
 148 void s_init(void)
 149 {
 150         /*
 151          * Undocumented magic taken from boot0, without this DRAM
 152          * access gets messed up (seems cache related).
 153          * The boot0 sources describe this as: "config ema for cache sram"
 154          */
 155 #if defined CONFIG_MACH_SUN6I
 156         setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
 157 #elif defined CONFIG_MACH_SUN8I
 158         __maybe_unused uint version;
 159
 160         /* Unlock sram version info reg, read it, relock */
 161         setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
 162         version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
 163         clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
 164
 165         /*
 166          * Ideally this would be a switch case, but we do not know exactly
 167          * which versions there are and which version needs which settings,
 168          * so reproduce the per SoC code from the BSP.
 169          */
 170 #if defined CONFIG_MACH_SUN8I_A23
 171         if (version == 0x1650)
 172                 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
 173         else /* 0x1661 ? */
 174                 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
 175 #elif defined CONFIG_MACH_SUN8I_A33
 176         if (version != 0x1667)
 177                 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
 178 #endif
 179         /* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */
 180         /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
 181 #endif
 182
 183 #if defined CONFIG_MACH_SUN6I || \
 184     defined CONFIG_MACH_SUN7I || \
 185     defined CONFIG_MACH_SUN8I || \
 186     defined CONFIG_MACH_SUN9I
 187         /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
 188         asm volatile(
 189                 "mrc p15, 0, r0, c1, c0, 1\n"
 190                 "orr r0, r0, #1 << 6\n"
 191                 "mcr p15, 0, r0, c1, c0, 1\n");
 192 #endif
 193 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
 194         /* Enable non-secure access to some peripherals */
 195         tzpc_init();
 196 #endif
 197
 198         clock_init();
 199         timer_init();
 200         gpio_init();
 201         i2c_init_board();
 202         eth_init_board();
 203 }
 204
 205 #ifdef CONFIG_SPL_BUILD
 206 DECLARE_GLOBAL_DATA_PTR;
 207
 208 /* The sunxi internal brom will try to loader external bootloader
 209  * from mmc0, nand flash, mmc2.
 210  */
 211 u32 spl_boot_device(void)
 212 {
 213         int boot_source;
 214
 215         /*
 216          * When booting from the SD card or NAND memory, the "eGON.BT0"
 217          * signature is expected to be found in memory at the address 0x0004
 218          * (see the "mksunxiboot" tool, which generates this header).
 219          *
 220          * When booting in the FEL mode over USB, this signature is patched in
 221          * memory and replaced with something else by the 'fel' tool. This other
 222          * signature is selected in such a way, that it can't be present in a
 223          * valid bootable SD card image (because the BROM would refuse to
 224          * execute the SPL in this case).
 225          *
 226          * This checks for the signature and if it is not found returns to
 227          * the FEL code in the BROM to wait and receive the main u-boot
 228          * binary over USB. If it is found, it determines where SPL was
 229          * read from.
 230          */
 231         if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
 232                 return BOOT_DEVICE_BOARD;
 233
 234         boot_source = readb(SPL_ADDR + 0x28);
 235         switch (boot_source) {
 236         case SUNXI_BOOTED_FROM_MMC0:
 237                 return BOOT_DEVICE_MMC1;
 238         case SUNXI_BOOTED_FROM_NAND:
 239                 return BOOT_DEVICE_NAND;
 240         case SUNXI_BOOTED_FROM_MMC2:
 241                 return BOOT_DEVICE_MMC2;
 242         case SUNXI_BOOTED_FROM_SPI:
 243                 return BOOT_DEVICE_SPI;
 244         }
 245
 246         panic("Unknown boot source %d\n", boot_source);
 247         return -1;              /* Never reached */
 248 }
 249
 250 /*
 251  * Properly announce BOOT_DEVICE_BOARD as "FEL".
 252  * Overrides weak function from common/spl/spl.c
 253  */
 254 void spl_board_announce_boot_device(void)
 255 {
 256         printf("FEL");
 257 }
 258
 259 /* No confirmation data available in SPL yet. Hardcode bootmode */
 260 u32 spl_boot_mode(const u32 boot_device)
 261 {
 262         return MMCSD_MODE_RAW;
 263 }
 264
 265 void board_init_f(ulong dummy)
 266 {
 267         spl_init();
 268         preloader_console_init();
 269
 270 #ifdef CONFIG_SPL_I2C_SUPPORT
 271         /* Needed early by sunxi_board_init if PMU is enabled */
 272         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 273 #endif
 274         sunxi_board_init();
 275 }
 276 #endif
 277
 278 void reset_cpu(ulong addr)
 279 {
 280 #ifdef CONFIG_SUNXI_GEN_SUN4I
 281         static const struct sunxi_wdog *wdog =
 282                  &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
 283
 284         /* Set the watchdog for its shortest interval (.5s) and wait */
 285         writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
 286         writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
 287
 288         while (1) {
 289                 /* sun5i sometimes gets stuck without this */
 290                 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
 291         }
 292 #endif
 293 #ifdef CONFIG_SUNXI_GEN_SUN6I
 294         static const struct sunxi_wdog *wdog =
 295                  ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
 296
 297         /* Set the watchdog for its shortest interval (.5s) and wait */
 298         writel(WDT_CFG_RESET, &wdog->cfg);
 299         writel(WDT_MODE_EN, &wdog->mode);
 300         writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
 301         while (1) { }
 302 #endif
 303 }
 304
 305 #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
 306 void enable_caches(void)
 307 {
 308         /* Enable D-cache. I-cache is already enabled in start.S */
 309         dcache_enable();
 310 }
 311 #endif