arch/arm/mach-tegra/board.c

   1 /*
   2  *  (C) Copyright 2010-2014
   3  *  NVIDIA Corporation <www.nvidia.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <spl.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/funcmux.h>
  13 #include <asm/arch/mc.h>
  14 #include <asm/arch/tegra.h>
  15 #include <asm/arch-tegra/ap.h>
  16 #include <asm/arch-tegra/board.h>
  17 #include <asm/arch-tegra/pmc.h>
  18 #include <asm/arch-tegra/sys_proto.h>
  19 #include <asm/arch-tegra/warmboot.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 enum {
  24         /* UARTs which we can enable */
  25         UARTA   = 1 << 0,
  26         UARTB   = 1 << 1,
  27         UARTC   = 1 << 2,
  28         UARTD   = 1 << 3,
  29         UARTE   = 1 << 4,
  30         UART_COUNT = 5,
  31 };
  32
  33 static bool from_spl __attribute__ ((section(".data")));
  34
  35 #ifndef CONFIG_SPL_BUILD
  36 void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
  37 {
  38         from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL;
  39         save_boot_params_ret();
  40 }
  41 #endif
  42
  43 bool spl_was_boot_source(void)
  44 {
  45         return from_spl;
  46 }
  47
  48 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
  49 #if !defined(CONFIG_TEGRA124)
  50 #error tegra_cpu_is_non_secure has only been validated on Tegra124
  51 #endif
  52 bool tegra_cpu_is_non_secure(void)
  53 {
  54         /*
  55          * This register reads 0xffffffff in non-secure mode. This register
  56          * only implements bits 31:20, so the lower bits will always read 0 in
  57          * secure mode. Thus, the lower bits are an indicator for secure vs.
  58          * non-secure mode.
  59          */
  60         struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
  61         uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0);
  62         return (mc_s_cfg0 & 1) == 1;
  63 }
  64 #endif
  65
  66 /* Read the RAM size directly from the memory controller */
  67 unsigned int query_sdram_size(void)
  68 {
  69         struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
  70         u32 emem_cfg, size_bytes;
  71
  72         emem_cfg = readl(&mc->mc_emem_cfg);
  73 #if defined(CONFIG_TEGRA20)
  74         debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg);
  75         size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024);
  76 #else
  77         debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg);
  78         /*
  79          * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits
  80          * and will wrap. Clip the reported size to the maximum that a 32-bit
  81          * variable can represent (rounded to a page).
  82          */
  83         if (emem_cfg >= 4096) {
  84                 size_bytes = U32_MAX & ~(0x1000 - 1);
  85         } else {
  86                 /* RAM size EMC is programmed to. */
  87                 size_bytes = emem_cfg * 1024 * 1024;
  88                 /*
  89                  * If all RAM fits within 32-bits, it can be accessed without
  90                  * LPAE, so go test the RAM size. Otherwise, we can't access
  91                  * all the RAM, and get_ram_size() would get confused, so
  92                  * avoid using it. There's no reason we should need this
  93                  * validation step anyway.
  94                  */
  95                 if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024))
  96                         size_bytes = get_ram_size((void *)PHYS_SDRAM_1,
  97                                                   size_bytes);
  98         }
  99 #endif
 100
 101 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
 102         /* External memory limited to 2047 MB due to IROM/HI-VEC */
 103         if (size_bytes == SZ_2G)
 104                 size_bytes -= SZ_1M;
 105 #endif
 106
 107         return size_bytes;
 108 }
 109
 110 int dram_init(void)
 111 {
 112         /* We do not initialise DRAM here. We just query the size */
 113         gd->ram_size = query_sdram_size();
 114         return 0;
 115 }
 116
 117 static int uart_configs[] = {
 118 #if defined(CONFIG_TEGRA20)
 119  #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
 120         FUNCMUX_UART1_UAA_UAB,
 121  #elif defined(CONFIG_TEGRA_UARTA_GPU)
 122         FUNCMUX_UART1_GPU,
 123  #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
 124         FUNCMUX_UART1_SDIO1,
 125  #else
 126         FUNCMUX_UART1_IRRX_IRTX,
 127 #endif
 128         FUNCMUX_UART2_UAD,
 129         -1,
 130         FUNCMUX_UART4_GMC,
 131         -1,
 132 #elif defined(CONFIG_TEGRA30)
 133         FUNCMUX_UART1_ULPI,     /* UARTA */
 134         -1,
 135         -1,
 136         -1,
 137         -1,
 138 #elif defined(CONFIG_TEGRA114)
 139         -1,
 140         -1,
 141         -1,
 142         FUNCMUX_UART4_GMI,      /* UARTD */
 143         -1,
 144 #else   /* Tegra124 */
 145         FUNCMUX_UART1_KBC,      /* UARTA */
 146         -1,
 147         -1,
 148         FUNCMUX_UART4_GPIO,     /* UARTD */
 149         -1,
 150 #endif
 151 };
 152
 153 /**
 154  * Set up the specified uarts
 155  *
 156  * @param uarts_ids     Mask containing UARTs to init (UARTx)
 157  */
 158 static void setup_uarts(int uart_ids)
 159 {
 160         static enum periph_id id_for_uart[] = {
 161                 PERIPH_ID_UART1,
 162                 PERIPH_ID_UART2,
 163                 PERIPH_ID_UART3,
 164                 PERIPH_ID_UART4,
 165                 PERIPH_ID_UART5,
 166         };
 167         size_t i;
 168
 169         for (i = 0; i < UART_COUNT; i++) {
 170                 if (uart_ids & (1 << i)) {
 171                         enum periph_id id = id_for_uart[i];
 172
 173                         funcmux_select(id, uart_configs[i]);
 174                         clock_ll_start_uart(id);
 175                 }
 176         }
 177 }
 178
 179 void board_init_uart_f(void)
 180 {
 181         int uart_ids = 0;       /* bit mask of which UART ids to enable */
 182
 183 #ifdef CONFIG_TEGRA_ENABLE_UARTA
 184         uart_ids |= UARTA;
 185 #endif
 186 #ifdef CONFIG_TEGRA_ENABLE_UARTB
 187         uart_ids |= UARTB;
 188 #endif
 189 #ifdef CONFIG_TEGRA_ENABLE_UARTC
 190         uart_ids |= UARTC;
 191 #endif
 192 #ifdef CONFIG_TEGRA_ENABLE_UARTD
 193         uart_ids |= UARTD;
 194 #endif
 195 #ifdef CONFIG_TEGRA_ENABLE_UARTE
 196         uart_ids |= UARTE;
 197 #endif
 198         setup_uarts(uart_ids);
 199 }
 200
 201 #ifndef CONFIG_SYS_DCACHE_OFF
 202 void enable_caches(void)
 203 {
 204         /* Enable D-cache. I-cache is already enabled in start.S */
 205         dcache_enable();
 206 }
 207 #endif