2 * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
9 #include <asm/arch/clock.h>
10 #include <asm/arch/gp_padctrl.h>
11 #include <asm/arch/pinmux.h>
12 #include <asm/arch/tegra.h>
13 #include <asm/arch-tegra/clk_rst.h>
14 #include <asm/arch-tegra/pmc.h>
15 #include <asm/arch-tegra/scu.h>
18 int get_num_cpus(void)
20 struct apb_misc_gp_ctlr
*gp
;
22 debug("%s entry\n", __func__
);
24 gp
= (struct apb_misc_gp_ctlr
*)NV_PA_APB_MISC_GP_BASE
;
25 rev
= (readl(&gp
->hidrev
) & HIDREV_CHIPID_MASK
) >> HIDREV_CHIPID_SHIFT
;
42 * Timing tables for each SOC for all four oscillator options.
44 struct clk_pll_table tegra_pll_x_table
[TEGRA_SOC_CNT
][CLOCK_OSC_FREQ_COUNT
] = {
48 * Register Field Bits Width
49 * ------------------------------
51 * PLLX_BASE n 17: 8 10
53 * PLLX_MISC cpcon 11: 8 4
56 { .n
= 1000, .m
= 13, .p
= 0, .cpcon
= 12 }, /* OSC: 13.0 MHz */
57 { .n
= 625, .m
= 12, .p
= 0, .cpcon
= 8 }, /* OSC: 19.2 MHz */
58 { .n
= 1000, .m
= 12, .p
= 0, .cpcon
= 12 }, /* OSC: 12.0 MHz */
59 { .n
= 1000, .m
= 26, .p
= 0, .cpcon
= 12 }, /* OSC: 26.0 MHz */
60 { .n
= 0, .m
= 0, .p
= 0, .cpcon
= 0 }, /* OSC: 38.4 MHz (N/A) */
61 { .n
= 0, .m
= 0, .p
= 0, .cpcon
= 0 }, /* OSC: 48.0 MHz (N/A) */
66 * Register Field Bits Width
67 * ------------------------------
69 * PLLX_BASE n 17: 8 10
71 * PLLX_MISC cpcon 11: 8 4
74 { .n
= 923, .m
= 10, .p
= 0, .cpcon
= 12 }, /* OSC: 13.0 MHz */
75 { .n
= 750, .m
= 12, .p
= 0, .cpcon
= 8 }, /* OSC: 19.2 MHz */
76 { .n
= 600, .m
= 6, .p
= 0, .cpcon
= 12 }, /* OSC: 12.0 MHz */
77 { .n
= 600, .m
= 13, .p
= 0, .cpcon
= 12 }, /* OSC: 26.0 MHz */
78 { .n
= 0, .m
= 0, .p
= 0, .cpcon
= 0 }, /* OSC: 38.4 MHz (N/A) */
79 { .n
= 0, .m
= 0, .p
= 0, .cpcon
= 0 }, /* OSC: 48.0 MHz (N/A) */
84 * Register Field Bits Width
85 * ------------------------------
87 * PLLX_BASE n 17: 8 10
89 * PLLX_MISC cpcon 11: 8 4
92 { .n
= 600, .m
= 13, .p
= 0, .cpcon
= 8 }, /* OSC: 13.0 MHz */
93 { .n
= 500, .m
= 16, .p
= 0, .cpcon
= 8 }, /* OSC: 19.2 MHz */
94 { .n
= 600, .m
= 12, .p
= 0, .cpcon
= 8 }, /* OSC: 12.0 MHz */
95 { .n
= 600, .m
= 26, .p
= 0, .cpcon
= 8 }, /* OSC: 26.0 MHz */
96 { .n
= 0, .m
= 0, .p
= 0, .cpcon
= 0 }, /* OSC: 38.4 MHz (N/A) */
97 { .n
= 0, .m
= 0, .p
= 0, .cpcon
= 0 }, /* OSC: 48.0 MHz (N/A) */
102 * Register Field Bits Width
103 * ------------------------------
104 * PLLX_BASE p 23:20 4
105 * PLLX_BASE n 15: 8 8
109 { .n
= 108, .m
= 1, .p
= 1 }, /* OSC: 13.0 MHz */
110 { .n
= 73, .m
= 1, .p
= 1 }, /* OSC: 19.2 MHz */
111 { .n
= 116, .m
= 1, .p
= 1 }, /* OSC: 12.0 MHz */
112 { .n
= 108, .m
= 2, .p
= 1 }, /* OSC: 26.0 MHz */
113 { .n
= 0, .m
= 0, .p
= 0 }, /* OSC: 38.4 MHz (N/A) */
114 { .n
= 0, .m
= 0, .p
= 0 }, /* OSC: 48.0 MHz (N/A) */
120 * Register Field Bits Width
121 * ------------------------------
122 * PLLX_BASE p 23:20 4
123 * PLLX_BASE n 15: 8 8
127 { .n
= 108, .m
= 1, .p
= 1 }, /* OSC: 13.0 MHz */
128 { .n
= 73, .m
= 1, .p
= 1 }, /* OSC: 19.2 MHz */
129 { .n
= 116, .m
= 1, .p
= 1 }, /* OSC: 12.0 MHz */
130 { .n
= 108, .m
= 2, .p
= 1 }, /* OSC: 26.0 MHz */
131 { .n
= 0, .m
= 0, .p
= 0 }, /* OSC: 38.4 MHz (N/A) */
132 { .n
= 0, .m
= 0, .p
= 0 }, /* OSC: 48.0 MHz (N/A) */
138 * Register Field Bits Width
139 * ------------------------------
140 * PLLX_BASE p 24:20 5
141 * PLLX_BASE n 15: 8 8
145 { .n
= 108, .m
= 1, .p
= 1 }, /* OSC: 13.0 MHz = 702 MHz*/
146 { .n
= 73, .m
= 1, .p
= 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/
147 { .n
= 116, .m
= 1, .p
= 1 }, /* OSC: 12.0 MHz = 696 MHz*/
148 { .n
= 108, .m
= 2, .p
= 1 }, /* OSC: 26.0 MHz = 702 MHz*/
149 { .n
= 36, .m
= 1, .p
= 1 }, /* OSC: 38.4 MHz = 691.2 MHz */
150 { .n
= 58, .m
= 2, .p
= 1 }, /* OSC: 48.0 MHz = 696 MHz */
154 static inline void pllx_set_iddq(void)
156 #if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
157 struct clk_rst_ctlr
*clkrst
= (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE
;
159 debug("%s entry\n", __func__
);
162 reg
= readl(&clkrst
->crc_pllx_misc3
);
163 reg
&= ~PLLX_IDDQ_MASK
;
164 writel(reg
, &clkrst
->crc_pllx_misc3
);
166 debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__
,
167 readl(&clkrst
->crc_pllx_misc3
));
171 int pllx_set_rate(struct clk_pll_simple
*pll
, u32 divn
, u32 divm
,
174 struct clk_pll_info
*pllinfo
= &tegra_pll_info_table
[CLOCK_ID_XCPU
];
175 int chip
= tegra_get_chip();
177 debug("%s entry\n", __func__
);
179 /* If PLLX is already enabled, just return */
180 if (readl(&pll
->pll_base
) & PLL_ENABLE_MASK
) {
181 debug("%s: PLLX already enabled, returning\n", __func__
);
187 /* Set BYPASS, m, n and p to PLLX_BASE */
188 reg
= PLL_BYPASS_MASK
| (divm
<< pllinfo
->m_shift
);
189 reg
|= (divn
<< pllinfo
->n_shift
) | (divp
<< pllinfo
->p_shift
);
190 writel(reg
, &pll
->pll_base
);
192 /* Set cpcon to PLLX_MISC */
193 if (chip
== CHIPID_TEGRA20
|| chip
== CHIPID_TEGRA30
)
194 reg
= (cpcon
<< pllinfo
->kcp_shift
);
199 * TODO(twarren@nvidia.com) Check which SoCs use DCCON
200 * and add to pllinfo table if needed!
202 /* Set dccon to PLLX_MISC if freq > 600MHz */
204 reg
|= (1 << PLL_DCCON_SHIFT
);
205 writel(reg
, &pll
->pll_misc
);
208 reg
= readl(&pll
->pll_base
);
209 reg
&= ~PLL_BYPASS_MASK
;
210 writel(reg
, &pll
->pll_base
);
211 debug("%s: base = 0x%08X\n", __func__
, reg
);
213 /* Set lock_enable to PLLX_MISC if lock_ena is valid (i.e. 0-31) */
214 reg
= readl(&pll
->pll_misc
);
215 if (pllinfo
->lock_ena
< 32)
216 reg
|= (1 << pllinfo
->lock_ena
);
217 writel(reg
, &pll
->pll_misc
);
218 debug("%s: misc = 0x%08X\n", __func__
, reg
);
220 /* Enable PLLX last, once it's all configured */
221 reg
= readl(&pll
->pll_base
);
222 reg
|= PLL_ENABLE_MASK
;
223 writel(reg
, &pll
->pll_base
);
224 debug("%s: base final = 0x%08X\n", __func__
, reg
);
231 struct clk_rst_ctlr
*clkrst
= (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE
;
232 struct clk_pll_simple
*pll
= &clkrst
->crc_pll_simple
[SIMPLE_PLLX
];
233 int soc_type
, sku_info
, chip_sku
;
234 enum clock_osc_freq osc
;
235 struct clk_pll_table
*sel
;
236 debug("%s entry\n", __func__
);
238 /* get SOC (chip) type */
239 soc_type
= tegra_get_chip();
240 debug("%s: SoC = 0x%02X\n", __func__
, soc_type
);
243 sku_info
= tegra_get_sku_info();
244 debug("%s: SKU info byte = 0x%02X\n", __func__
, sku_info
);
246 /* get chip SKU, combo of the above info */
247 chip_sku
= tegra_get_chip_sku();
248 debug("%s: Chip SKU = %d\n", __func__
, chip_sku
);
251 osc
= clock_get_osc_freq();
252 debug("%s: osc = %d\n", __func__
, osc
);
255 sel
= &tegra_pll_x_table
[chip_sku
][osc
];
256 pllx_set_rate(pll
, sel
->n
, sel
->m
, sel
->p
, sel
->cpcon
);
259 void enable_cpu_clock(int enable
)
261 struct clk_rst_ctlr
*clkrst
= (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE
;
263 debug("%s entry\n", __func__
);
267 * Regardless of whether the request is to enable or disable the CPU
268 * clock, every processor in the CPU complex except the master (CPU 0)
269 * will have it's clock stopped because the AVP only talks to the
274 /* Initialize PLLX */
277 /* Wait until all clocks are stable */
278 udelay(PLL_STABILIZATION_DELAY
);
280 writel(CCLK_BURST_POLICY
, &clkrst
->crc_cclk_brst_pol
);
281 writel(SUPER_CCLK_DIVIDER
, &clkrst
->crc_super_cclk_div
);
285 * Read the register containing the individual CPU clock enables and
286 * always stop the clocks to CPUs > 0.
288 clk
= readl(&clkrst
->crc_clk_cpu_cmplx
);
289 clk
|= 1 << CPU1_CLK_STP_SHIFT
;
290 if (get_num_cpus() == 4)
291 clk
|= (1 << CPU2_CLK_STP_SHIFT
) + (1 << CPU3_CLK_STP_SHIFT
);
293 /* Stop/Unstop the CPU clock */
294 clk
&= ~CPU0_CLK_STP_MASK
;
295 clk
|= !enable
<< CPU0_CLK_STP_SHIFT
;
296 writel(clk
, &clkrst
->crc_clk_cpu_cmplx
);
298 clock_enable(PERIPH_ID_CPU
);
301 static int is_cpu_powered(void)
303 struct pmc_ctlr
*pmc
= (struct pmc_ctlr
*)NV_PA_PMC_BASE
;
305 return (readl(&pmc
->pmc_pwrgate_status
) & CPU_PWRED
) ? 1 : 0;
308 static void remove_cpu_io_clamps(void)
310 struct pmc_ctlr
*pmc
= (struct pmc_ctlr
*)NV_PA_PMC_BASE
;
312 debug("%s entry\n", __func__
);
314 /* Remove the clamps on the CPU I/O signals */
315 reg
= readl(&pmc
->pmc_remove_clamping
);
317 writel(reg
, &pmc
->pmc_remove_clamping
);
319 /* Give I/O signals time to stabilize */
320 udelay(IO_STABILIZATION_DELAY
);
323 void powerup_cpu(void)
325 struct pmc_ctlr
*pmc
= (struct pmc_ctlr
*)NV_PA_PMC_BASE
;
327 int timeout
= IO_STABILIZATION_DELAY
;
328 debug("%s entry\n", __func__
);
330 if (!is_cpu_powered()) {
331 /* Toggle the CPU power state (OFF -> ON) */
332 reg
= readl(&pmc
->pmc_pwrgate_toggle
);
335 writel(reg
, &pmc
->pmc_pwrgate_toggle
);
337 /* Wait for the power to come up */
338 while (!is_cpu_powered()) {
340 printf("CPU failed to power up!\n");
346 * Remove the I/O clamps from CPU power partition.
347 * Recommended only on a Warm boot, if the CPU partition gets
348 * power gated. Shouldn't cause any harm when called after a
349 * cold boot according to HW, probably just redundant.
351 remove_cpu_io_clamps();
355 void reset_A9_cpu(int reset
)
358 * NOTE: Regardless of whether the request is to hold the CPU in reset
359 * or take it out of reset, every processor in the CPU complex
360 * except the master (CPU 0) will be held in reset because the
361 * AVP only talks to the master. The AVP does not know that there
362 * are multiple processors in the CPU complex.
364 int mask
= crc_rst_cpu
| crc_rst_de
| crc_rst_debug
;
365 int num_cpus
= get_num_cpus();
368 debug("%s entry\n", __func__
);
369 /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
370 for (cpu
= 1; cpu
< num_cpus
; cpu
++)
371 reset_cmplx_set_enable(cpu
, mask
, 1);
372 reset_cmplx_set_enable(0, mask
, reset
);
374 /* Enable/Disable master CPU reset */
375 reset_set_enable(PERIPH_ID_CPU
, reset
);
378 void clock_enable_coresight(int enable
)
382 debug("%s entry\n", __func__
);
383 clock_set_enable(PERIPH_ID_CORESIGHT
, enable
);
384 reset_set_enable(PERIPH_ID_CORESIGHT
, !enable
);
388 * Put CoreSight on PLLP_OUT0 and divide it down as per
389 * PLLP base frequency based on SoC type (T20/T30+).
390 * Clock divider request would setup CSITE clock as 144MHz
391 * for PLLP base 216MHz and 204MHz for PLLP base 408MHz
393 src
= CLK_DIVIDER(NVBL_PLLP_KHZ
, CSITE_KHZ
);
394 clock_ll_set_source_divisor(PERIPH_ID_CSI
, 0, src
);
396 /* Unlock the CPU CoreSight interfaces */
397 rst
= CORESIGHT_UNLOCK
;
398 writel(rst
, CSITE_CPU_DBG0_LAR
);
399 writel(rst
, CSITE_CPU_DBG1_LAR
);
400 if (get_num_cpus() == 4) {
401 writel(rst
, CSITE_CPU_DBG2_LAR
);
402 writel(rst
, CSITE_CPU_DBG3_LAR
);
409 debug("%s entry\n", __func__
);
412 writel(HALT_COP_EVENT_JTAG
| (FLOW_MODE_STOP
<< 29),
413 FLOW_CTLR_HALT_COP_EVENTS
);