arch/arm/mach-tegra/tegra114/clock.c

   1 /*
   2  * (C) Copyright 2010-2015
   3  * NVIDIA Corporation <www.nvidia.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /* Tegra114 Clock control functions */
   9
  10 #include <common.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/sysctr.h>
  14 #include <asm/arch/tegra.h>
  15 #include <asm/arch-tegra/clk_rst.h>
  16 #include <asm/arch-tegra/timer.h>
  17 #include <div64.h>
  18 #include <fdtdec.h>
  19
  20 /*
  21  * Clock types that we can use as a source. The Tegra114 has muxes for the
  22  * peripheral clocks, and in most cases there are four options for the clock
  23  * source. This gives us a clock 'type' and exploits what commonality exists
  24  * in the device.
  25  *
  26  * Letters are obvious, except for T which means CLK_M, and S which means the
  27  * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
  28  * datasheet) and PLL_M are different things. The former is the basic
  29  * clock supplied to the SOC from an external oscillator. The latter is the
  30  * memory clock PLL.
  31  *
  32  * See definitions in clock_id in the header file.
  33  */
  34 enum clock_type_id {
  35         CLOCK_TYPE_AXPT,        /* PLL_A, PLL_X, PLL_P, CLK_M */
  36         CLOCK_TYPE_MCPA,        /* and so on */
  37         CLOCK_TYPE_MCPT,
  38         CLOCK_TYPE_PCM,
  39         CLOCK_TYPE_PCMT,
  40         CLOCK_TYPE_PCMT16,
  41         CLOCK_TYPE_PDCT,
  42         CLOCK_TYPE_ACPT,
  43         CLOCK_TYPE_ASPTE,
  44         CLOCK_TYPE_PMDACD2T,
  45         CLOCK_TYPE_PCST,
  46
  47         CLOCK_TYPE_COUNT,
  48         CLOCK_TYPE_NONE = -1,   /* invalid clock type */
  49 };
  50
  51 enum {
  52         CLOCK_MAX_MUX   = 8     /* number of source options for each clock */
  53 };
  54
  55 /*
  56  * Clock source mux for each clock type. This just converts our enum into
  57  * a list of mux sources for use by the code.
  58  *
  59  * Note:
  60  *  The extra column in each clock source array is used to store the mask
  61  *  bits in its register for the source.
  62  */
  63 #define CLK(x) CLOCK_ID_ ## x
  64 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
  65         { CLK(AUDIO),   CLK(XCPU),      CLK(PERIPH),    CLK(OSC),
  66                 CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
  67                 MASK_BITS_31_30},
  68         { CLK(MEMORY),  CLK(CGENERAL),  CLK(PERIPH),    CLK(AUDIO),
  69                 CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
  70                 MASK_BITS_31_30},
  71         { CLK(MEMORY),  CLK(CGENERAL),  CLK(PERIPH),    CLK(OSC),
  72                 CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
  73                 MASK_BITS_31_30},
  74         { CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(NONE),
  75                 CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
  76                 MASK_BITS_31_30},
  77         { CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(OSC),
  78                 CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
  79                 MASK_BITS_31_30},
  80         { CLK(PERIPH),  CLK(CGENERAL),  CLK(MEMORY),    CLK(OSC),
  81                 CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
  82                 MASK_BITS_31_30},
  83         { CLK(PERIPH),  CLK(DISPLAY),   CLK(CGENERAL),  CLK(OSC),
  84                 CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
  85                 MASK_BITS_31_30},
  86         { CLK(AUDIO),   CLK(CGENERAL),  CLK(PERIPH),    CLK(OSC),
  87                 CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
  88                 MASK_BITS_31_30},
  89         { CLK(AUDIO),   CLK(SFROM32KHZ),        CLK(PERIPH),    CLK(OSC),
  90                 CLK(EPCI),      CLK(NONE),      CLK(NONE),      CLK(NONE),
  91                 MASK_BITS_31_29},
  92         { CLK(PERIPH),  CLK(MEMORY),    CLK(DISPLAY),   CLK(AUDIO),
  93                 CLK(CGENERAL),  CLK(DISPLAY2),  CLK(OSC),       CLK(NONE),
  94                 MASK_BITS_31_29},
  95         { CLK(PERIPH),  CLK(CGENERAL),  CLK(SFROM32KHZ),        CLK(OSC),
  96                 CLK(NONE),      CLK(NONE),      CLK(NONE),      CLK(NONE),
  97                 MASK_BITS_31_28}
  98 };
  99
 100 /*
 101  * Clock type for each peripheral clock source. We put the name in each
 102  * record just so it is easy to match things up
 103  */
 104 #define TYPE(name, type) type
 105 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
 106         /* 0x00 */
 107         TYPE(PERIPHC_I2S1,      CLOCK_TYPE_AXPT),
 108         TYPE(PERIPHC_I2S2,      CLOCK_TYPE_AXPT),
 109         TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
 110         TYPE(PERIPHC_SPDIF_IN,  CLOCK_TYPE_PCM),
 111         TYPE(PERIPHC_PWM,       CLOCK_TYPE_PCST),  /* only PWM uses b29:28 */
 112         TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
 113         TYPE(PERIPHC_SBC2,      CLOCK_TYPE_PCMT),
 114         TYPE(PERIPHC_SBC3,      CLOCK_TYPE_PCMT),
 115
 116         /* 0x08 */
 117         TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
 118         TYPE(PERIPHC_I2C1,      CLOCK_TYPE_PCMT16),
 119         TYPE(PERIPHC_I2C5,      CLOCK_TYPE_PCMT16),
 120         TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
 121         TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
 122         TYPE(PERIPHC_SBC1,      CLOCK_TYPE_PCMT),
 123         TYPE(PERIPHC_DISP1,     CLOCK_TYPE_PMDACD2T),
 124         TYPE(PERIPHC_DISP2,     CLOCK_TYPE_PMDACD2T),
 125
 126         /* 0x10 */
 127         TYPE(PERIPHC_CVE,       CLOCK_TYPE_PDCT),
 128         TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
 129         TYPE(PERIPHC_VI,        CLOCK_TYPE_MCPA),
 130         TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
 131         TYPE(PERIPHC_SDMMC1,    CLOCK_TYPE_PCMT),
 132         TYPE(PERIPHC_SDMMC2,    CLOCK_TYPE_PCMT),
 133         TYPE(PERIPHC_G3D,       CLOCK_TYPE_MCPA),
 134         TYPE(PERIPHC_G2D,       CLOCK_TYPE_MCPA),
 135
 136         /* 0x18 */
 137         TYPE(PERIPHC_NDFLASH,   CLOCK_TYPE_PCMT),
 138         TYPE(PERIPHC_SDMMC4,    CLOCK_TYPE_PCMT),
 139         TYPE(PERIPHC_VFIR,      CLOCK_TYPE_PCMT),
 140         TYPE(PERIPHC_EPP,       CLOCK_TYPE_MCPA),
 141         TYPE(PERIPHC_MPE,       CLOCK_TYPE_MCPA),
 142         TYPE(PERIPHC_MIPI,      CLOCK_TYPE_PCMT),       /* MIPI base-band HSI */
 143         TYPE(PERIPHC_UART1,     CLOCK_TYPE_PCMT),
 144         TYPE(PERIPHC_UART2,     CLOCK_TYPE_PCMT),
 145
 146         /* 0x20 */
 147         TYPE(PERIPHC_HOST1X,    CLOCK_TYPE_MCPA),
 148         TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
 149         TYPE(PERIPHC_TVO,       CLOCK_TYPE_PDCT),
 150         TYPE(PERIPHC_HDMI,      CLOCK_TYPE_PMDACD2T),
 151         TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
 152         TYPE(PERIPHC_TVDAC,     CLOCK_TYPE_PDCT),
 153         TYPE(PERIPHC_I2C2,      CLOCK_TYPE_PCMT16),
 154         TYPE(PERIPHC_EMC,       CLOCK_TYPE_MCPT),
 155
 156         /* 0x28 */
 157         TYPE(PERIPHC_UART3,     CLOCK_TYPE_PCMT),
 158         TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
 159         TYPE(PERIPHC_VI,        CLOCK_TYPE_MCPA),
 160         TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
 161         TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
 162         TYPE(PERIPHC_SBC4,      CLOCK_TYPE_PCMT),
 163         TYPE(PERIPHC_I2C3,      CLOCK_TYPE_PCMT16),
 164         TYPE(PERIPHC_SDMMC3,    CLOCK_TYPE_PCMT),
 165
 166         /* 0x30 */
 167         TYPE(PERIPHC_UART4,     CLOCK_TYPE_PCMT),
 168         TYPE(PERIPHC_UART5,     CLOCK_TYPE_PCMT),
 169         TYPE(PERIPHC_VDE,       CLOCK_TYPE_PCMT),
 170         TYPE(PERIPHC_OWR,       CLOCK_TYPE_PCMT),
 171         TYPE(PERIPHC_NOR,       CLOCK_TYPE_PCMT),
 172         TYPE(PERIPHC_CSITE,     CLOCK_TYPE_PCMT),
 173         TYPE(PERIPHC_I2S0,      CLOCK_TYPE_AXPT),
 174         TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
 175
 176         /* 0x38h */  /* Jumps to reg offset 0x3B0h */
 177         TYPE(PERIPHC_G3D2,      CLOCK_TYPE_MCPA),
 178         TYPE(PERIPHC_MSELECT,   CLOCK_TYPE_PCMT),
 179         TYPE(PERIPHC_TSENSOR,   CLOCK_TYPE_PCST),       /* s/b PCTS */
 180         TYPE(PERIPHC_I2S3,      CLOCK_TYPE_AXPT),
 181         TYPE(PERIPHC_I2S4,      CLOCK_TYPE_AXPT),
 182         TYPE(PERIPHC_I2C4,      CLOCK_TYPE_PCMT16),
 183         TYPE(PERIPHC_SBC5,      CLOCK_TYPE_PCMT),
 184         TYPE(PERIPHC_SBC6,      CLOCK_TYPE_PCMT),
 185
 186         /* 0x40 */
 187         TYPE(PERIPHC_AUDIO,     CLOCK_TYPE_ACPT),
 188         TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
 189         TYPE(PERIPHC_DAM0,      CLOCK_TYPE_ACPT),
 190         TYPE(PERIPHC_DAM1,      CLOCK_TYPE_ACPT),
 191         TYPE(PERIPHC_DAM2,      CLOCK_TYPE_ACPT),
 192         TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PCMT),
 193         TYPE(PERIPHC_ACTMON,    CLOCK_TYPE_PCST),       /* MASK 31:30 */
 194         TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
 195
 196         /* 0x48 */
 197         TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
 198         TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
 199         TYPE(PERIPHC_NANDSPEED, CLOCK_TYPE_PCMT),
 200         TYPE(PERIPHC_I2CSLOW,   CLOCK_TYPE_PCST),       /* MASK 31:30 */
 201         TYPE(PERIPHC_SYS,       CLOCK_TYPE_NONE),
 202         TYPE(PERIPHC_SPEEDO,    CLOCK_TYPE_PCMT),
 203         TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
 204         TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
 205
 206         /* 0x50 */
 207         TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
 208         TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
 209         TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
 210         TYPE(PERIPHC_NONE,      CLOCK_TYPE_NONE),
 211         TYPE(PERIPHC_SATAOOB,   CLOCK_TYPE_PCMT),       /* offset 0x420h */
 212         TYPE(PERIPHC_SATA,      CLOCK_TYPE_PCMT),
 213         TYPE(PERIPHC_HDA,       CLOCK_TYPE_PCMT),
 214 };
 215
 216 /*
 217  * This array translates a periph_id to a periphc_internal_id
 218  *
 219  * Not present/matched up:
 220  *      uint vi_sensor;  _VI_SENSOR_0,          0x1A8
 221  *      SPDIF - which is both 0x08 and 0x0c
 222  *
 223  */
 224 #define NONE(name) (-1)
 225 #define OFFSET(name, value) PERIPHC_ ## name
 226 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
 227         /* Low word: 31:0 */
 228         NONE(CPU),
 229         NONE(COP),
 230         NONE(TRIGSYS),
 231         NONE(RESERVED3),
 232         NONE(RTC),
 233         NONE(TMR),
 234         PERIPHC_UART1,
 235         PERIPHC_UART2,  /* and vfir 0x68 */
 236
 237         /* 8 */
 238         NONE(GPIO),
 239         PERIPHC_SDMMC2,
 240         NONE(SPDIF),            /* 0x08 and 0x0c, unclear which to use */
 241         PERIPHC_I2S1,
 242         PERIPHC_I2C1,
 243         PERIPHC_NDFLASH,
 244         PERIPHC_SDMMC1,
 245         PERIPHC_SDMMC4,
 246
 247         /* 16 */
 248         NONE(RESERVED16),
 249         PERIPHC_PWM,
 250         PERIPHC_I2S2,
 251         PERIPHC_EPP,
 252         PERIPHC_VI,
 253         PERIPHC_G2D,
 254         NONE(USBD),
 255         NONE(ISP),
 256
 257         /* 24 */
 258         PERIPHC_G3D,
 259         NONE(RESERVED25),
 260         PERIPHC_DISP2,
 261         PERIPHC_DISP1,
 262         PERIPHC_HOST1X,
 263         NONE(VCP),
 264         PERIPHC_I2S0,
 265         NONE(CACHE2),
 266
 267         /* Middle word: 63:32 */
 268         NONE(MEM),
 269         NONE(AHBDMA),
 270         NONE(APBDMA),
 271         NONE(RESERVED35),
 272         NONE(RESERVED36),
 273         NONE(STAT_MON),
 274         NONE(RESERVED38),
 275         NONE(RESERVED39),
 276
 277         /* 40 */
 278         NONE(KFUSE),
 279         NONE(SBC1),     /* SBC1, 0x34, is this SPI1? */
 280         PERIPHC_NOR,
 281         NONE(RESERVED43),
 282         PERIPHC_SBC2,
 283         NONE(RESERVED45),
 284         PERIPHC_SBC3,
 285         PERIPHC_I2C5,
 286
 287         /* 48 */
 288         NONE(DSI),
 289         PERIPHC_TVO,    /* also CVE 0x40 */
 290         PERIPHC_MIPI,
 291         PERIPHC_HDMI,
 292         NONE(CSI),
 293         PERIPHC_TVDAC,
 294         PERIPHC_I2C2,
 295         PERIPHC_UART3,
 296
 297         /* 56 */
 298         NONE(RESERVED56),
 299         PERIPHC_EMC,
 300         NONE(USB2),
 301         NONE(USB3),
 302         PERIPHC_MPE,
 303         PERIPHC_VDE,
 304         NONE(BSEA),
 305         NONE(BSEV),
 306
 307         /* Upper word 95:64 */
 308         PERIPHC_SPEEDO,
 309         PERIPHC_UART4,
 310         PERIPHC_UART5,
 311         PERIPHC_I2C3,
 312         PERIPHC_SBC4,
 313         PERIPHC_SDMMC3,
 314         NONE(PCIE),
 315         PERIPHC_OWR,
 316
 317         /* 72 */
 318         NONE(AFI),
 319         PERIPHC_CSITE,
 320         NONE(PCIEXCLK),
 321         NONE(AVPUCQ),
 322         NONE(RESERVED76),
 323         NONE(RESERVED77),
 324         NONE(RESERVED78),
 325         NONE(DTV),
 326
 327         /* 80 */
 328         PERIPHC_NANDSPEED,
 329         PERIPHC_I2CSLOW,
 330         NONE(DSIB),
 331         NONE(RESERVED83),
 332         NONE(IRAMA),
 333         NONE(IRAMB),
 334         NONE(IRAMC),
 335         NONE(IRAMD),
 336
 337         /* 88 */
 338         NONE(CRAM2),
 339         NONE(RESERVED89),
 340         NONE(MDOUBLER),
 341         NONE(RESERVED91),
 342         NONE(SUSOUT),
 343         NONE(RESERVED93),
 344         NONE(RESERVED94),
 345         NONE(RESERVED95),
 346
 347         /* V word: 31:0 */
 348         NONE(CPUG),
 349         NONE(CPULP),
 350         PERIPHC_G3D2,
 351         PERIPHC_MSELECT,
 352         PERIPHC_TSENSOR,
 353         PERIPHC_I2S3,
 354         PERIPHC_I2S4,
 355         PERIPHC_I2C4,
 356
 357         /* 08 */
 358         PERIPHC_SBC5,
 359         PERIPHC_SBC6,
 360         PERIPHC_AUDIO,
 361         NONE(APBIF),
 362         PERIPHC_DAM0,
 363         PERIPHC_DAM1,
 364         PERIPHC_DAM2,
 365         PERIPHC_HDA2CODEC2X,
 366
 367         /* 16 */
 368         NONE(ATOMICS),
 369         NONE(RESERVED17),
 370         NONE(RESERVED18),
 371         NONE(RESERVED19),
 372         NONE(RESERVED20),
 373         NONE(RESERVED21),
 374         NONE(RESERVED22),
 375         PERIPHC_ACTMON,
 376
 377         /* 24 */
 378         NONE(RESERVED24),
 379         NONE(RESERVED25),
 380         NONE(RESERVED26),
 381         NONE(RESERVED27),
 382         PERIPHC_SATA,
 383         PERIPHC_HDA,
 384         NONE(RESERVED30),
 385         NONE(RESERVED31),
 386
 387         /* W word: 31:0 */
 388         NONE(HDA2HDMICODEC),
 389         NONE(RESERVED1_SATACOLD),
 390         NONE(RESERVED2_PCIERX0),
 391         NONE(RESERVED3_PCIERX1),
 392         NONE(RESERVED4_PCIERX2),
 393         NONE(RESERVED5_PCIERX3),
 394         NONE(RESERVED6_PCIERX4),
 395         NONE(RESERVED7_PCIERX5),
 396
 397         /* 40 */
 398         NONE(CEC),
 399         NONE(PCIE2_IOBIST),
 400         NONE(EMC_IOBIST),
 401         NONE(HDMI_IOBIST),
 402         NONE(SATA_IOBIST),
 403         NONE(MIPI_IOBIST),
 404         NONE(EMC1_IOBIST),
 405         NONE(XUSB),
 406
 407         /* 48 */
 408         NONE(CILAB),
 409         NONE(CILCD),
 410         NONE(CILE),
 411         NONE(DSIA_LP),
 412         NONE(DSIB_LP),
 413         NONE(RESERVED21_ENTROPY),
 414         NONE(RESERVED22_W),
 415         NONE(RESERVED23_W),
 416
 417         /* 56 */
 418         NONE(RESERVED24_W),
 419         NONE(AMX0),
 420         NONE(ADX0),
 421         NONE(DVFS),
 422         NONE(XUSB_SS),
 423         NONE(EMC_DLL),
 424         NONE(MC1),
 425         NONE(EMC1),
 426 };
 427
 428 /*
 429  * PLL divider shift/mask tables for all PLL IDs.
 430  */
 431 struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
 432         /*
 433          * T114: some deviations from T2x/T30.
 434          * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.)
 435          *       If lock_ena or lock_det are >31, they're not used in that PLL.
 436          */
 437
 438         { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF,  .p_shift = 20, .p_mask = 0x0F,
 439           .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 },   /* PLLC */
 440         { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF,  .p_shift = 0,  .p_mask = 0,
 441           .lock_ena = 0,  .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 },     /* PLLM */
 442         { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
 443           .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */
 444         { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
 445           .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLA */
 446         { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
 447           .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLU */
 448         { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
 449           .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */
 450         { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF,  .p_shift = 20, .p_mask = 0x0F,
 451           .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 },     /* PLLX */
 452         { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF,  .p_shift = 0,  .p_mask = 0,
 453           .lock_ena = 9,  .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 },     /* PLLE */
 454         { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
 455           .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */
 456 };
 457
 458 /*
 459  * Get the oscillator frequency, from the corresponding hardware configuration
 460  * field. Note that T30/T114 support 3 new higher freqs, but we map back
 461  * to the old T20 freqs. Support for the higher oscillators is TBD.
 462  */
 463 enum clock_osc_freq clock_get_osc_freq(void)
 464 {
 465         struct clk_rst_ctlr *clkrst =
 466                         (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
 467         u32 reg;
 468
 469         reg = readl(&clkrst->crc_osc_ctrl);
 470         reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
 471
 472         if (reg & 1)                            /* one of the newer freqs */
 473                 printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
 474
 475         return reg >> 2;        /* Map to most common (T20) freqs */
 476 }
 477
 478 /* Returns a pointer to the clock source register for a peripheral */
 479 u32 *get_periph_source_reg(enum periph_id periph_id)
 480 {
 481         struct clk_rst_ctlr *clkrst =
 482                 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
 483         enum periphc_internal_id internal_id;
 484
 485         /* Coresight is a special case */
 486         if (periph_id == PERIPH_ID_CSI)
 487                 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
 488
 489         assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
 490         internal_id = periph_id_to_internal_id[periph_id];
 491         assert(internal_id != -1);
 492         if (internal_id >= PERIPHC_VW_FIRST) {
 493                 internal_id -= PERIPHC_VW_FIRST;
 494                 return &clkrst->crc_clk_src_vw[internal_id];
 495         } else
 496                 return &clkrst->crc_clk_src[internal_id];
 497 }
 498
 499 /**
 500  * Given a peripheral ID and the required source clock, this returns which
 501  * value should be programmed into the source mux for that peripheral.
 502  *
 503  * There is special code here to handle the one source type with 5 sources.
 504  *
 505  * @param periph_id     peripheral to start
 506  * @param source        PLL id of required parent clock
 507  * @param mux_bits      Set to number of bits in mux register: 2 or 4
 508  * @param divider_bits Set to number of divider bits (8 or 16)
 509  * @return mux value (0-4, or -1 if not found)
 510  */
 511 int get_periph_clock_source(enum periph_id periph_id,
 512         enum clock_id parent, int *mux_bits, int *divider_bits)
 513 {
 514         enum clock_type_id type;
 515         enum periphc_internal_id internal_id;
 516         int mux;
 517
 518         assert(clock_periph_id_isvalid(periph_id));
 519
 520         internal_id = periph_id_to_internal_id[periph_id];
 521         assert(periphc_internal_id_isvalid(internal_id));
 522
 523         type = clock_periph_type[internal_id];
 524         assert(clock_type_id_isvalid(type));
 525
 526         *mux_bits = clock_source[type][CLOCK_MAX_MUX];
 527
 528         if (type == CLOCK_TYPE_PCMT16)
 529                 *divider_bits = 16;
 530         else
 531                 *divider_bits = 8;
 532
 533         for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
 534                 if (clock_source[type][mux] == parent)
 535                         return mux;
 536
 537         /* if we get here, either us or the caller has made a mistake */
 538         printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
 539                 parent);
 540         return -1;
 541 }
 542
 543 void clock_set_enable(enum periph_id periph_id, int enable)
 544 {
 545         struct clk_rst_ctlr *clkrst =
 546                 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
 547         u32 *clk;
 548         u32 reg;
 549
 550         /* Enable/disable the clock to this peripheral */
 551         assert(clock_periph_id_isvalid(periph_id));
 552         if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
 553                 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
 554         else
 555                 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
 556         reg = readl(clk);
 557         if (enable)
 558                 reg |= PERIPH_MASK(periph_id);
 559         else
 560                 reg &= ~PERIPH_MASK(periph_id);
 561         writel(reg, clk);
 562 }
 563
 564 void reset_set_enable(enum periph_id periph_id, int enable)
 565 {
 566         struct clk_rst_ctlr *clkrst =
 567                 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
 568         u32 *reset;
 569         u32 reg;
 570
 571         /* Enable/disable reset to the peripheral */
 572         assert(clock_periph_id_isvalid(periph_id));
 573         if (periph_id < PERIPH_ID_VW_FIRST)
 574                 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
 575         else
 576                 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
 577         reg = readl(reset);
 578         if (enable)
 579                 reg |= PERIPH_MASK(periph_id);
 580         else
 581                 reg &= ~PERIPH_MASK(periph_id);
 582         writel(reg, reset);
 583 }
 584
 585 #if CONFIG_IS_ENABLED(OF_CONTROL)
 586 /*
 587  * Convert a device tree clock ID to our peripheral ID. They are mostly
 588  * the same but we are very cautious so we check that a valid clock ID is
 589  * provided.
 590  *
 591  * @param clk_id    Clock ID according to tegra114 device tree binding
 592  * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
 593  */
 594 enum periph_id clk_id_to_periph_id(int clk_id)
 595 {
 596         if (clk_id > PERIPH_ID_COUNT)
 597                 return PERIPH_ID_NONE;
 598
 599         switch (clk_id) {
 600         case PERIPH_ID_RESERVED3:
 601         case PERIPH_ID_RESERVED16:
 602         case PERIPH_ID_RESERVED24:
 603         case PERIPH_ID_RESERVED35:
 604         case PERIPH_ID_RESERVED43:
 605         case PERIPH_ID_RESERVED45:
 606         case PERIPH_ID_RESERVED56:
 607         case PERIPH_ID_RESERVED76:
 608         case PERIPH_ID_RESERVED77:
 609         case PERIPH_ID_RESERVED78:
 610         case PERIPH_ID_RESERVED83:
 611         case PERIPH_ID_RESERVED89:
 612         case PERIPH_ID_RESERVED91:
 613         case PERIPH_ID_RESERVED93:
 614         case PERIPH_ID_RESERVED94:
 615         case PERIPH_ID_RESERVED95:
 616                 return PERIPH_ID_NONE;
 617         default:
 618                 return clk_id;
 619         }
 620 }
 621 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
 622
 623 void clock_early_init(void)
 624 {
 625         struct clk_rst_ctlr *clkrst =
 626                 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
 627         struct clk_pll_info *pllinfo;
 628         u32 data;
 629
 630         tegra30_set_up_pllp();
 631
 632         /* clear IDDQ before accessing any other PLLC registers */
 633         pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL];
 634         clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ);
 635         udelay(2);
 636
 637         /*
 638          * PLLC output frequency set to 600Mhz
 639          * PLLD output frequency set to 925Mhz
 640          */
 641         switch (clock_get_osc_freq()) {
 642         case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
 643                 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
 644                 clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
 645                 break;
 646
 647         case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
 648                 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
 649                 clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
 650                 break;
 651
 652         case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
 653                 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
 654                 clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
 655                 break;
 656         case CLOCK_OSC_FREQ_19_2:
 657         default:
 658                 /*
 659                  * These are not supported. It is too early to print a
 660                  * message and the UART likely won't work anyway due to the
 661                  * oscillator being wrong.
 662                  */
 663                 break;
 664         }
 665
 666         /* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */
 667         writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);
 668
 669         /* PLLC_MISC: Set LOCK_ENABLE */
 670         pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL];
 671         setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena));
 672         udelay(2);
 673
 674         /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1, and enable lock */
 675         pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY];
 676         data = (12 << pllinfo->kcp_shift) | (1 << pllinfo->kvco_shift);
 677         data |= (1 << PLLD_CLKENABLE) | (1 << pllinfo->lock_ena);
 678         writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
 679         udelay(2);
 680 }
 681
 682 void arch_timer_init(void)
 683 {
 684         struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
 685         u32 freq, val;
 686
 687         freq = clock_get_rate(CLOCK_ID_CLK_M);
 688         debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq);
 689
 690         /* ARM CNTFRQ */
 691         asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
 692
 693         /* Only T114 has the System Counter regs */
 694         debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
 695         writel(freq, &sysctr->cntfid0);
 696
 697         val = readl(&sysctr->cntcr);
 698         val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
 699         writel(val, &sysctr->cntcr);
 700         debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
 701 }