2 * Copyright (c) 2011 The Chromium OS Authors.
4 * SPDX-License-Identifier: GPL-2.0+
7 /* Tegra20 pin multiplexing functions */
11 #include <asm/arch/pinmux.h>
14 * This defines the order of the pin mux control bits in the registers. For
15 * some reason there is no correspendence between the tristate, pin mux and
16 * pullup/pulldown registers.
19 /* 0: APB_MISC_PP_PIN_MUX_CTL_A_0 */
38 /* 16: APB_MISC_PP_PIN_MUX_CTL_B_0 */
57 /* 32: APB_MISC_PP_PIN_MUX_CTL_C_0 */
76 /* 48: APB_MISC_PP_PIN_MUX_CTL_D_0 */
95 /* 64: APB_MISC_PP_PIN_MUX_CTL_E_0 */
114 /* 80: APB_MISC_PP_PIN_MUX_CTL_F_0 */
133 /* 96: APB_MISC_PP_PIN_MUX_CTL_G_0 */
156 * And this defines the order of the pullup/pulldown controls which are again
157 * in a different order
160 /* 0: APB_MISC_PP_PULLUPDOWN_REG_A_0 */
179 /* 16: APB_MISC_PP_PULLUPDOWN_REG_B_0 */
197 /* 32: APB_MISC_PP_PULLUPDOWN_REG_C_0 */
216 /* 48: APB_MISC_PP_PULLUPDOWN_REG_D_0 */
235 /* 64: APB_MISC_PP_PULLUPDOWN_REG_E_0 */
257 /* Convenient macro for defining pin group properties */
258 #define PINALL(pingrp, f0, f1, f2, f3, mux, pupd) \
270 /* A normal pin group where the mux name and pull-up name match */
271 #define PIN(pingrp, f0, f1, f2, f3) \
272 PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pingrp)
274 /* A pin group where the pull-up name doesn't have a 1-1 mapping */
275 #define PINP(pingrp, f0, f1, f2, f3, pupd) \
276 PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pupd)
278 /* A pin group number which is not used */
279 #define PIN_RESERVED \
280 PIN(NONE, RSVD1, RSVD2, RSVD3, RSVD4)
282 #define DRVGRP(drvgrp) \
283 PINALL(drvgrp, RSVD1, RSVD2, RSVD3, RSVD4, MUXCTL_NONE, PUCTL_NONE)
285 static const struct pmux_pingrp_desc tegra20_pingroups
[] = {
286 PIN(ATA
, IDE
, NAND
, GMI
, RSVD4
),
287 PIN(ATB
, IDE
, NAND
, GMI
, SDIO4
),
288 PIN(ATC
, IDE
, NAND
, GMI
, SDIO4
),
289 PIN(ATD
, IDE
, NAND
, GMI
, SDIO4
),
290 PIN(CDEV1
, OSC
, PLLA_OUT
, PLLM_OUT1
, AUDIO_SYNC
),
291 PIN(CDEV2
, OSC
, AHB_CLK
, APB_CLK
, PLLP_OUT4
),
292 PIN(CSUS
, PLLC_OUT1
, PLLP_OUT2
, PLLP_OUT3
, VI_SENSOR_CLK
),
293 PIN(DAP1
, DAP1
, RSVD2
, GMI
, SDIO2
),
295 PIN(DAP2
, DAP2
, TWC
, RSVD3
, GMI
),
296 PIN(DAP3
, DAP3
, RSVD2
, RSVD3
, RSVD4
),
297 PIN(DAP4
, DAP4
, RSVD2
, GMI
, RSVD4
),
298 PIN(DTA
, RSVD1
, SDIO2
, VI
, RSVD4
),
299 PIN(DTB
, RSVD1
, RSVD2
, VI
, SPI1
),
300 PIN(DTC
, RSVD1
, RSVD2
, VI
, RSVD4
),
301 PIN(DTD
, RSVD1
, SDIO2
, VI
, RSVD4
),
302 PIN(DTE
, RSVD1
, RSVD2
, VI
, SPI1
),
304 PINP(GPU
, PWM
, UARTA
, GMI
, RSVD4
, GPSLXAU
),
305 PIN(GPV
, PCIE
, RSVD2
, RSVD3
, RSVD4
),
306 PIN(I2CP
, I2C
, RSVD2
, RSVD3
, RSVD4
),
307 PIN(IRTX
, UARTA
, UARTB
, GMI
, SPI4
),
308 PIN(IRRX
, UARTA
, UARTB
, GMI
, SPI4
),
309 PIN(KBCB
, KBC
, NAND
, SDIO2
, MIO
),
310 PIN(KBCA
, KBC
, NAND
, SDIO2
, EMC_TEST0_DLL
),
311 PINP(PMC
, PWR_ON
, PWR_INTR
, RSVD3
, RSVD4
, NONE
),
313 PIN(PTA
, I2C2
, HDMI
, GMI
, RSVD4
),
314 PIN(RM
, I2C
, RSVD2
, RSVD3
, RSVD4
),
315 PIN(KBCE
, KBC
, NAND
, OWR
, RSVD4
),
316 PIN(KBCF
, KBC
, NAND
, TRACE
, MIO
),
317 PIN(GMA
, UARTE
, SPI3
, GMI
, SDIO4
),
318 PIN(GMC
, UARTD
, SPI4
, GMI
, SFLASH
),
319 PIN(SDMMC1
, SDIO1
, RSVD2
, UARTE
, UARTA
),
320 PIN(OWC
, OWR
, RSVD2
, RSVD3
, RSVD4
),
322 PIN(GME
, RSVD1
, DAP5
, GMI
, SDIO4
),
323 PIN(SDC
, PWM
, TWC
, SDIO3
, SPI3
),
324 PIN(SDD
, UARTA
, PWM
, SDIO3
, SPI3
),
326 PINP(SLXA
, PCIE
, SPI4
, SDIO3
, SPI2
, CRTP
),
327 PIN(SLXC
, SPDIF
, SPI4
, SDIO3
, SPI2
),
328 PIN(SLXD
, SPDIF
, SPI4
, SDIO3
, SPI2
),
329 PIN(SLXK
, PCIE
, SPI4
, SDIO3
, SPI2
),
331 PIN(SPDI
, SPDIF
, RSVD2
, I2C
, SDIO2
),
332 PIN(SPDO
, SPDIF
, RSVD2
, I2C
, SDIO2
),
333 PIN(SPIA
, SPI1
, SPI2
, SPI3
, GMI
),
334 PIN(SPIB
, SPI1
, SPI2
, SPI3
, GMI
),
335 PIN(SPIC
, SPI1
, SPI2
, SPI3
, GMI
),
336 PIN(SPID
, SPI2
, SPI1
, SPI2_ALT
, GMI
),
337 PIN(SPIE
, SPI2
, SPI1
, SPI2_ALT
, GMI
),
338 PIN(SPIF
, SPI3
, SPI1
, SPI2
, RSVD4
),
340 PIN(SPIG
, SPI3
, SPI2
, SPI2_ALT
, I2C
),
341 PIN(SPIH
, SPI3
, SPI2
, SPI2_ALT
, I2C
),
342 PIN(UAA
, SPI3
, MIPI_HS
, UARTA
, ULPI
),
343 PIN(UAB
, SPI2
, MIPI_HS
, UARTA
, ULPI
),
344 PIN(UAC
, OWR
, RSVD2
, RSVD3
, RSVD4
),
345 PIN(UAD
, UARTB
, SPDIF
, UARTA
, SPI4
),
346 PIN(UCA
, UARTC
, RSVD2
, GMI
, RSVD4
),
347 PIN(UCB
, UARTC
, PWM
, GMI
, RSVD4
),
350 PIN(ATE
, IDE
, NAND
, GMI
, RSVD4
),
351 PIN(KBCC
, KBC
, NAND
, TRACE
, EMC_TEST1_DLL
),
354 PIN(GMB
, IDE
, NAND
, GMI
, GMI_INT
),
355 PIN(GMD
, RSVD1
, NAND
, GMI
, SFLASH
),
356 PIN(DDC
, I2C2
, RSVD2
, RSVD3
, RSVD4
),
359 PINP(LD0
, DISPA
, DISPB
, XIO
, RSVD4
, LD17
),
360 PINP(LD1
, DISPA
, DISPB
, XIO
, RSVD4
, LD17
),
361 PINP(LD2
, DISPA
, DISPB
, XIO
, RSVD4
, LD17
),
362 PINP(LD3
, DISPA
, DISPB
, XIO
, RSVD4
, LD17
),
363 PINP(LD4
, DISPA
, DISPB
, XIO
, RSVD4
, LD17
),
364 PINP(LD5
, DISPA
, DISPB
, XIO
, RSVD4
, LD17
),
365 PINP(LD6
, DISPA
, DISPB
, XIO
, RSVD4
, LD17
),
366 PINP(LD7
, DISPA
, DISPB
, XIO
, RSVD4
, LD17
),
368 PINP(LD8
, DISPA
, DISPB
, XIO
, RSVD4
, LD17
),
369 PINP(LD9
, DISPA
, DISPB
, XIO
, RSVD4
, LD17
),
370 PINP(LD10
, DISPA
, DISPB
, XIO
, RSVD4
, LD17
),
371 PINP(LD11
, DISPA
, DISPB
, XIO
, RSVD4
, LD17
),
372 PINP(LD12
, DISPA
, DISPB
, XIO
, RSVD4
, LD17
),
373 PINP(LD13
, DISPA
, DISPB
, XIO
, RSVD4
, LD17
),
374 PINP(LD14
, DISPA
, DISPB
, XIO
, RSVD4
, LD17
),
375 PINP(LD15
, DISPA
, DISPB
, XIO
, RSVD4
, LD17
),
377 PINP(LD16
, DISPA
, DISPB
, XIO
, RSVD4
, LD17
),
378 PINP(LD17
, DISPA
, DISPB
, RSVD3
, RSVD4
, LD17
),
379 PINP(LHP0
, DISPA
, DISPB
, RSVD3
, RSVD4
, LD21_20
),
380 PINP(LHP1
, DISPA
, DISPB
, RSVD3
, RSVD4
, LD19_18
),
381 PINP(LHP2
, DISPA
, DISPB
, RSVD3
, RSVD4
, LD19_18
),
382 PINP(LVP0
, DISPA
, DISPB
, RSVD3
, RSVD4
, LC
),
383 PINP(LVP1
, DISPA
, DISPB
, RSVD3
, RSVD4
, LD21_20
),
384 PINP(HDINT
, HDMI
, RSVD2
, RSVD3
, RSVD4
, LC
),
386 PINP(LM0
, DISPA
, DISPB
, SPI3
, RSVD4
, LC
),
387 PINP(LM1
, DISPA
, DISPB
, RSVD3
, CRT
, LC
),
388 PINP(LVS
, DISPA
, DISPB
, XIO
, RSVD4
, LC
),
389 PINP(LSC0
, DISPA
, DISPB
, XIO
, RSVD4
, LC
),
390 PINP(LSC1
, DISPA
, DISPB
, SPI3
, HDMI
, LS
),
391 PINP(LSCK
, DISPA
, DISPB
, SPI3
, HDMI
, LS
),
392 PINP(LDC
, DISPA
, DISPB
, RSVD3
, RSVD4
, LS
),
393 PINP(LCSN
, DISPA
, DISPB
, SPI3
, RSVD4
, LS
),
396 PINP(LSPI
, DISPA
, DISPB
, XIO
, HDMI
, LC
),
397 PINP(LSDA
, DISPA
, DISPB
, SPI3
, HDMI
, LS
),
398 PINP(LSDI
, DISPA
, DISPB
, SPI3
, RSVD4
, LS
),
399 PINP(LPW0
, DISPA
, DISPB
, SPI3
, HDMI
, LS
),
400 PINP(LPW1
, DISPA
, DISPB
, RSVD3
, RSVD4
, LS
),
401 PINP(LPW2
, DISPA
, DISPB
, SPI3
, HDMI
, LS
),
402 PINP(LDI
, DISPA
, DISPB
, RSVD3
, RSVD4
, LD23_22
),
403 PINP(LHS
, DISPA
, DISPB
, XIO
, RSVD4
, LC
),
405 PINP(LPP
, DISPA
, DISPB
, RSVD3
, RSVD4
, LD23_22
),
407 PIN(KBCD
, KBC
, NAND
, SDIO2
, MIO
),
408 PIN(GPU7
, RTCK
, RSVD2
, RSVD3
, RSVD4
),
409 PIN(DTF
, I2C3
, RSVD2
, VI
, RSVD4
),
410 PIN(UDA
, SPI1
, RSVD2
, UARTD
, ULPI
),
411 PIN(CRTP
, CRT
, RSVD2
, RSVD3
, RSVD4
),
412 PINP(SDB
, UARTA
, PWM
, SDIO3
, SPI2
, NONE
),
414 /* these pin groups only have pullup and pull down control */
425 const struct pmux_pingrp_desc
*tegra_soc_pingroups
= tegra20_pingroups
;