2 * (C) Copyright 2010 - 2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/flow.h>
12 #include <asm/arch/pinmux.h>
13 #include <asm/arch/tegra.h>
14 #include <asm/arch-tegra/ap.h>
15 #include <asm/arch-tegra/apb_misc.h>
16 #include <asm/arch-tegra/clk_rst.h>
17 #include <asm/arch-tegra/pmc.h>
18 #include <asm/arch-tegra/warmboot.h>
19 #include "warmboot_avp.h"
21 #define DEBUG_RESET_CORESIGHT
25 struct apb_misc_pp_ctlr
*apb_misc
=
26 (struct apb_misc_pp_ctlr
*)NV_PA_APB_MISC_BASE
;
27 struct pmc_ctlr
*pmc
= (struct pmc_ctlr
*)NV_PA_PMC_BASE
;
28 struct flow_ctlr
*flow
= (struct flow_ctlr
*)NV_PA_FLOW_BASE
;
29 struct clk_rst_ctlr
*clkrst
=
30 (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE
;
31 union osc_ctrl_reg osc_ctrl
;
32 union pllx_base_reg pllx_base
;
33 union pllx_misc_reg pllx_misc
;
34 union scratch3_reg scratch3
;
37 /* enable JTAG & TBE */
38 writel(CONFIG_CTL_TBE
| CONFIG_CTL_JTAG
, &apb_misc
->cfg_ctl
);
40 /* Are we running where we're supposed to be? */
42 "adr %0, wb_start;" /* reg: wb_start address */
43 : "=r"(reg
) /* output */
44 /* no input, no clobber list */
47 if (reg
!= NV_WB_RUN_ADDRESS
)
50 /* Are we running with AVP? */
51 if (readl(NV_PA_PG_UP_BASE
+ PG_UP_TAG_0
) != PG_UP_TAG_AVP
)
54 #ifdef DEBUG_RESET_CORESIGHT
55 /* Assert CoreSight reset */
56 reg
= readl(&clkrst
->crc_rst_dev
[TEGRA_DEV_U
]);
58 writel(reg
, &clkrst
->crc_rst_dev
[TEGRA_DEV_U
]);
61 /* TODO: Set the drive strength - maybe make this a board parameter? */
62 osc_ctrl
.word
= readl(&clkrst
->crc_osc_ctrl
);
65 writel(osc_ctrl
.word
, &clkrst
->crc_osc_ctrl
);
67 /* Power up the CPU complex if necessary */
68 if (!(readl(&pmc
->pmc_pwrgate_status
) & PWRGATE_STATUS_CPU
)) {
69 reg
= PWRGATE_TOGGLE_PARTID_CPU
| PWRGATE_TOGGLE_START
;
70 writel(reg
, &pmc
->pmc_pwrgate_toggle
);
71 while (!(readl(&pmc
->pmc_pwrgate_status
) & PWRGATE_STATUS_CPU
))
75 /* Remove the I/O clamps from the CPU power partition. */
76 reg
= readl(&pmc
->pmc_remove_clamping
);
78 writel(reg
, &pmc
->pmc_remove_clamping
);
80 reg
= EVENT_ZERO_VAL_20
| EVENT_MSEC
| EVENT_MODE_STOP
;
81 writel(reg
, &flow
->halt_cop_events
);
83 /* Assert CPU complex reset */
84 reg
= readl(&clkrst
->crc_rst_dev
[TEGRA_DEV_L
]);
86 writel(reg
, &clkrst
->crc_rst_dev
[TEGRA_DEV_L
]);
88 /* Hold both CPUs in reset */
89 reg
= CPU_CMPLX_CPURESET0
| CPU_CMPLX_CPURESET1
| CPU_CMPLX_DERESET0
|
90 CPU_CMPLX_DERESET1
| CPU_CMPLX_DBGRESET0
| CPU_CMPLX_DBGRESET1
;
91 writel(reg
, &clkrst
->crc_cpu_cmplx_set
);
93 /* Halt CPU1 at the flow controller for uni-processor configurations */
94 writel(EVENT_MODE_STOP
, &flow
->halt_cpu1_events
);
97 * Set the CPU reset vector. SCRATCH41 contains the physical
98 * address of the CPU-side restoration code.
100 reg
= readl(&pmc
->pmc_scratch41
);
101 writel(reg
, EXCEP_VECTOR_CPU_RESET_VECTOR
);
103 /* Select CPU complex clock source */
104 writel(CCLK_PLLP_BURST_POLICY
, &clkrst
->crc_cclk_brst_pol
);
106 /* Start the CPU0 clock and stop the CPU1 clock */
107 reg
= CPU_CMPLX_CPU_BRIDGE_CLKDIV_4
| CPU_CMPLX_CPU0_CLK_STP_RUN
|
108 CPU_CMPLX_CPU1_CLK_STP_STOP
;
109 writel(reg
, &clkrst
->crc_clk_cpu_cmplx
);
111 /* Enable the CPU complex clock */
112 reg
= readl(&clkrst
->crc_clk_out_enb
[TEGRA_DEV_L
]);
114 writel(reg
, &clkrst
->crc_clk_out_enb
[TEGRA_DEV_L
]);
116 /* Make sure the resets were held for at least 2 microseconds */
117 reg
= readl(TIMER_USEC_CNTR
);
118 while (readl(TIMER_USEC_CNTR
) <= (reg
+ 2))
121 #ifdef DEBUG_RESET_CORESIGHT
123 * De-assert CoreSight reset.
124 * NOTE: We're leaving the CoreSight clock on the oscillator for
125 * now. It will be restored to its original clock source
126 * when the CPU-side restoration code runs.
128 reg
= readl(&clkrst
->crc_rst_dev
[TEGRA_DEV_U
]);
129 reg
&= ~SWR_CSITE_RST
;
130 writel(reg
, &clkrst
->crc_rst_dev
[TEGRA_DEV_U
]);
133 /* Unlock the CPU CoreSight interfaces */
135 writel(reg
, CSITE_CPU_DBG0_LAR
);
136 writel(reg
, CSITE_CPU_DBG1_LAR
);
139 * Sample the microsecond timestamp again. This is the time we must
140 * use when returning from LP0 for PLL stabilization delays.
142 reg
= readl(TIMER_USEC_CNTR
);
143 writel(reg
, &pmc
->pmc_scratch1
);
147 scratch3
.word
= readl(&pmc
->pmc_scratch3
);
149 /* Get the OSC. For 19.2 MHz, use 19 to make the calculations easier */
150 reg
= (readl(TIMER_USEC_CFG
) & USEC_CFG_DIVISOR_MASK
) + 1;
153 * According to the TRM, for 19.2MHz OSC, the USEC_DIVISOR is 0x5f, and
154 * USEC_DIVIDEND is 0x04. So, if USEC_DIVISOR > 26, OSC is 19.2 MHz.
156 * reg is used to calculate the pllx freq, which is used to determine if
157 * to set dccon or not.
162 /* PLLX_BASE.PLLX_DIVM */
163 if (scratch3
.pllx_base_divm
== reg
)
168 /* PLLX_BASE.PLLX_DIVN */
169 pllx_base
.divn
= scratch3
.pllx_base_divn
;
170 reg
= scratch3
.pllx_base_divn
<< reg
;
172 /* PLLX_BASE.PLLX_DIVP */
173 pllx_base
.divp
= scratch3
.pllx_base_divp
;
174 reg
= reg
>> scratch3
.pllx_base_divp
;
176 pllx_base
.bypass
= 1;
178 /* PLLX_MISC_DCCON must be set for pllx frequency > 600 MHz. */
182 /* PLLX_MISC_LFCON */
183 pllx_misc
.lfcon
= scratch3
.pllx_misc_lfcon
;
185 /* PLLX_MISC_CPCON */
186 pllx_misc
.cpcon
= scratch3
.pllx_misc_cpcon
;
188 writel(pllx_misc
.word
, &clkrst
->crc_pll_simple
[SIMPLE_PLLX
].pll_misc
);
189 writel(pllx_base
.word
, &clkrst
->crc_pll_simple
[SIMPLE_PLLX
].pll_base
);
191 pllx_base
.enable
= 1;
192 writel(pllx_base
.word
, &clkrst
->crc_pll_simple
[SIMPLE_PLLX
].pll_base
);
193 pllx_base
.bypass
= 0;
194 writel(pllx_base
.word
, &clkrst
->crc_pll_simple
[SIMPLE_PLLX
].pll_base
);
196 writel(0, flow
->halt_cpu_events
);
198 reg
= CPU_CMPLX_CPURESET0
| CPU_CMPLX_DBGRESET0
| CPU_CMPLX_DERESET0
;
199 writel(reg
, &clkrst
->crc_cpu_cmplx_clr
);
201 reg
= PLLM_OUT1_RSTN_RESET_DISABLE
| PLLM_OUT1_CLKEN_ENABLE
|
202 PLLM_OUT1_RATIO_VAL_8
;
203 writel(reg
, &clkrst
->crc_pll
[CLOCK_ID_MEMORY
].pll_out
[0]);
205 reg
= SCLK_SWAKE_FIQ_SRC_PLLM_OUT1
| SCLK_SWAKE_IRQ_SRC_PLLM_OUT1
|
206 SCLK_SWAKE_RUN_SRC_PLLM_OUT1
| SCLK_SWAKE_IDLE_SRC_PLLM_OUT1
|
208 writel(reg
, &clkrst
->crc_sclk_brst_pol
);
210 /* avp_resume: no return after the write */
211 reg
= readl(&clkrst
->crc_rst_dev
[TEGRA_DEV_L
]);
213 writel(reg
, &clkrst
->crc_rst_dev
[TEGRA_DEV_L
]);
217 reg
= EVENT_MODE_STOP
| EVENT_JTAG
;
218 writel(reg
, flow
->halt_cop_events
);
223 * Execution comes here if something goes wrong. The chip is reset and
224 * a cold boot is performed.
226 writel(SWR_TRIG_SYS_RST
, &clkrst
->crc_rst_dev
[TEGRA_DEV_L
]);
231 * wb_end() is a dummy function, and must be directly following wb_start(),
232 * and is used to calculate the size of wb_start().