2 * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
9 #include <asm/arch/clock.h>
10 #include <asm/arch/flow.h>
11 #include <asm/arch/tegra.h>
12 #include <asm/arch-tegra/clk_rst.h>
13 #include <asm/arch-tegra/pmc.h>
14 #include <asm/arch-tegra/tegra_i2c.h>
17 /* Tegra30-specific CPU init code */
18 void tegra_i2c_ll_write_addr(uint addr
, uint config
)
20 struct i2c_ctlr
*reg
= (struct i2c_ctlr
*)TEGRA_DVC_BASE
;
22 writel(addr
, ®
->cmd_addr0
);
23 writel(config
, ®
->cnfg
);
26 void tegra_i2c_ll_write_data(uint data
, uint config
)
28 struct i2c_ctlr
*reg
= (struct i2c_ctlr
*)TEGRA_DVC_BASE
;
30 writel(data
, ®
->cmd_data1
);
31 writel(config
, ®
->cnfg
);
34 #define TPS62366A_I2C_ADDR 0xC0
35 #define TPS62366A_SET1_REG 0x01
36 #define TPS62366A_SET1_DATA (0x4600 | TPS62366A_SET1_REG)
38 #define TPS62361B_I2C_ADDR 0xC0
39 #define TPS62361B_SET3_REG 0x03
40 #define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG)
42 #define TPS65911_I2C_ADDR 0x5A
43 #define TPS65911_VDDCTRL_OP_REG 0x28
44 #define TPS65911_VDDCTRL_SR_REG 0x27
45 #define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG)
46 #define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
47 #define I2C_SEND_2_BYTES 0x0A02
49 static void enable_cpu_power_rail(void)
51 struct pmc_ctlr
*pmc
= (struct pmc_ctlr
*)NV_PA_PMC_BASE
;
54 debug("enable_cpu_power_rail entry\n");
55 reg
= readl(&pmc
->pmc_cntrl
);
57 writel(reg
, &pmc
->pmc_cntrl
);
59 /* Set VDD_CORE to 1.200V. */
60 #ifdef CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
61 tegra_i2c_ll_write_addr(TPS62366A_I2C_ADDR
, 2);
62 tegra_i2c_ll_write_data(TPS62366A_SET1_DATA
, I2C_SEND_2_BYTES
);
64 #ifdef CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
65 tegra_i2c_ll_write_addr(TPS62361B_I2C_ADDR
, 2);
66 tegra_i2c_ll_write_data(TPS62361B_SET3_DATA
, I2C_SEND_2_BYTES
);
71 * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
72 * First set VDD to 1.0125V, then enable the VDD regulator.
74 tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR
, 2);
75 tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA
, I2C_SEND_2_BYTES
);
77 tegra_i2c_ll_write_data(TPS65911_VDDCTRL_SR_DATA
, I2C_SEND_2_BYTES
);
82 * The T30 requires some special clock initialization, including setting up
83 * the dvc i2c, turning on mselect and selecting the G CPU cluster
85 void t30_init_clocks(void)
87 struct clk_rst_ctlr
*clkrst
=
88 (struct clk_rst_ctlr
*)NV_PA_CLK_RST_BASE
;
89 struct flow_ctlr
*flow
= (struct flow_ctlr
*)NV_PA_FLOW_BASE
;
92 debug("t30_init_clocks entry\n");
93 /* Set active CPU cluster to G */
94 clrbits_le32(flow
->cluster_control
, 1 << 0);
96 writel(SUPER_SCLK_ENB_MASK
, &clkrst
->crc_super_sclk_div
);
98 val
= (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT
) |
99 (1 << CLK_SYS_RATE_AHB_RATE_SHIFT
) |
100 (0 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT
) |
101 (0 << CLK_SYS_RATE_APB_RATE_SHIFT
);
102 writel(val
, &clkrst
->crc_clk_sys_rate
);
104 /* Put i2c, mselect in reset and enable clocks */
105 reset_set_enable(PERIPH_ID_DVC_I2C
, 1);
106 clock_set_enable(PERIPH_ID_DVC_I2C
, 1);
107 reset_set_enable(PERIPH_ID_MSELECT
, 1);
108 clock_set_enable(PERIPH_ID_MSELECT
, 1);
110 /* Switch MSELECT clock to PLLP (00) and use a divisor of 2 */
111 clock_ll_set_source_divisor(PERIPH_ID_MSELECT
, 0, 2);
114 * Our high-level clock routines are not available prior to
115 * relocation. We use the low-level functions which require a
116 * hard-coded divisor. Use CLK_M with divide by (n + 1 = 17)
118 clock_ll_set_source_divisor(PERIPH_ID_DVC_I2C
, 3, 16);
121 * Give clocks time to stabilize, then take i2c and mselect out of
125 reset_set_enable(PERIPH_ID_DVC_I2C
, 0);
126 reset_set_enable(PERIPH_ID_MSELECT
, 0);
129 static void set_cpu_running(int run
)
131 struct flow_ctlr
*flow
= (struct flow_ctlr
*)NV_PA_FLOW_BASE
;
133 debug("set_cpu_running entry, run = %d\n", run
);
134 writel(run
? FLOW_MODE_NONE
: FLOW_MODE_STOP
, &flow
->halt_cpu_events
);
137 void start_cpu(u32 reset_vector
)
139 debug("start_cpu entry, reset_vector = %x\n", reset_vector
);
143 enable_cpu_power_rail();
147 /* Hold the CPUs in reset */
150 /* Disable the CPU clock */
153 /* Enable CoreSight */
154 clock_enable_coresight(1);
157 * Set the entry point for CPU execution from reset,
158 * if it's a non-zero value.
161 writel(reset_vector
, EXCEP_VECTOR_CPU_RESET_VECTOR
);
163 /* Enable the CPU clock */
166 /* If the CPU doesn't already have power, power it up */
169 /* Take the CPU out of reset */