arch/arm/mach-uniphier/arm32/cache-uniphier.c

   1 /*
   2  * Copyright (C) 2012-2014 Panasonic Corporation
   3  * Copyright (C) 2015-2016 Socionext Inc.
   4  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <linux/io.h>
  11 #include <linux/kernel.h>
  12 #include <asm/armv7.h>
  13 #include <asm/processor.h>
  14
  15 #include "cache-uniphier.h"
  16
  17 /* control registers */
  18 #define UNIPHIER_SSCC           0x500c0000      /* Control Register */
  19 #define    UNIPHIER_SSCC_BST                    (0x1 << 20)     /* UCWG burst read */
  20 #define    UNIPHIER_SSCC_ACT                    (0x1 << 19)     /* Inst-Data separate */
  21 #define    UNIPHIER_SSCC_WTG                    (0x1 << 18)     /* WT gathering on */
  22 #define    UNIPHIER_SSCC_PRD                    (0x1 << 17)     /* enable pre-fetch */
  23 #define    UNIPHIER_SSCC_ON                     (0x1 <<  0)     /* enable cache */
  24 #define UNIPHIER_SSCLPDAWCR     0x500c0030      /* Unified/Data Active Way Control */
  25 #define UNIPHIER_SSCLPIAWCR     0x500c0034      /* Instruction Active Way Control */
  26
  27 /* revision registers */
  28 #define UNIPHIER_SSCID          0x503c0100      /* ID Register */
  29
  30 /* operation registers */
  31 #define UNIPHIER_SSCOPE         0x506c0244      /* Cache Operation Primitive Entry */
  32 #define    UNIPHIER_SSCOPE_CM_INV               0x0     /* invalidate */
  33 #define    UNIPHIER_SSCOPE_CM_CLEAN             0x1     /* clean */
  34 #define    UNIPHIER_SSCOPE_CM_FLUSH             0x2     /* flush */
  35 #define    UNIPHIER_SSCOPE_CM_SYNC              0x8     /* sync (drain bufs) */
  36 #define    UNIPHIER_SSCOPE_CM_FLUSH_PREFETCH    0x9     /* flush p-fetch buf */
  37 #define UNIPHIER_SSCOQM         0x506c0248
  38 #define    UNIPHIER_SSCOQM_TID_MASK             (0x3 << 21)
  39 #define    UNIPHIER_SSCOQM_TID_LRU_DATA         (0x0 << 21)
  40 #define    UNIPHIER_SSCOQM_TID_LRU_INST         (0x1 << 21)
  41 #define    UNIPHIER_SSCOQM_TID_WAY              (0x2 << 21)
  42 #define    UNIPHIER_SSCOQM_S_MASK               (0x3 << 17)
  43 #define    UNIPHIER_SSCOQM_S_RANGE              (0x0 << 17)
  44 #define    UNIPHIER_SSCOQM_S_ALL                (0x1 << 17)
  45 #define    UNIPHIER_SSCOQM_S_WAY                (0x2 << 17)
  46 #define    UNIPHIER_SSCOQM_CE                   (0x1 << 15)     /* notify completion */
  47 #define    UNIPHIER_SSCOQM_CW                   (0x1 << 14)
  48 #define    UNIPHIER_SSCOQM_CM_MASK              (0x7)
  49 #define    UNIPHIER_SSCOQM_CM_INV               0x0     /* invalidate */
  50 #define    UNIPHIER_SSCOQM_CM_CLEAN             0x1     /* clean */
  51 #define    UNIPHIER_SSCOQM_CM_FLUSH             0x2     /* flush */
  52 #define    UNIPHIER_SSCOQM_CM_PREFETCH          0x3     /* prefetch to cache */
  53 #define    UNIPHIER_SSCOQM_CM_PREFETCH_BUF      0x4     /* prefetch to pf-buf */
  54 #define    UNIPHIER_SSCOQM_CM_TOUCH             0x5     /* touch */
  55 #define    UNIPHIER_SSCOQM_CM_TOUCH_ZERO        0x6     /* touch to zero */
  56 #define    UNIPHIER_SSCOQM_CM_TOUCH_DIRTY       0x7     /* touch with dirty */
  57 #define UNIPHIER_SSCOQAD        0x506c024c      /* Cache Operation Queue Address */
  58 #define UNIPHIER_SSCOQSZ        0x506c0250      /* Cache Operation Queue Size */
  59 #define UNIPHIER_SSCOQMASK      0x506c0254      /* Cache Operation Queue Address Mask */
  60 #define UNIPHIER_SSCOQWN        0x506c0258      /* Cache Operation Queue Way Number */
  61 #define UNIPHIER_SSCOPPQSEF     0x506c025c      /* Cache Operation Queue Set Complete */
  62 #define    UNIPHIER_SSCOPPQSEF_FE               (0x1 << 1)
  63 #define    UNIPHIER_SSCOPPQSEF_OE               (0x1 << 0)
  64 #define UNIPHIER_SSCOLPQS       0x506c0260      /* Cache Operation Queue Status */
  65 #define    UNIPHIER_SSCOLPQS_EF                 (0x1 << 2)
  66 #define    UNIPHIER_SSCOLPQS_EST                (0x1 << 1)
  67 #define    UNIPHIER_SSCOLPQS_QST                (0x1 << 0)
  68
  69 #define UNIPHIER_SSC_LINE_SIZE          128
  70 #define UNIPHIER_SSC_RANGE_OP_MAX_SIZE  (0x00400000 - (UNIPHIER_SSC_LINE_SIZE))
  71
  72 #define UNIPHIER_SSCOQAD_IS_NEEDED(op) \
  73                 ((op & UNIPHIER_SSCOQM_S_MASK) == UNIPHIER_SSCOQM_S_RANGE)
  74 #define UNIPHIER_SSCOQWM_IS_NEEDED(op) \
  75                 ((op & UNIPHIER_SSCOQM_TID_MASK) == UNIPHIER_SSCOQM_TID_WAY)
  76
  77 /* uniphier_cache_sync - perform a sync point for a particular cache level */
  78 static void uniphier_cache_sync(void)
  79 {
  80         /* drain internal buffers */
  81         writel(UNIPHIER_SSCOPE_CM_SYNC, UNIPHIER_SSCOPE);
  82         /* need a read back to confirm */
  83         readl(UNIPHIER_SSCOPE);
  84 }
  85
  86 /**
  87  * uniphier_cache_maint_common - run a queue operation
  88  *
  89  * @start: start address of range operation (don't care for "all" operation)
  90  * @size: data size of range operation (don't care for "all" operation)
  91  * @ways: target ways (don't care for operations other than pre-fetch, touch
  92  * @operation: flags to specify the desired cache operation
  93  */
  94 static void uniphier_cache_maint_common(u32 start, u32 size, u32 ways,
  95                                         u32 operation)
  96 {
  97         /* clear the complete notification flag */
  98         writel(UNIPHIER_SSCOLPQS_EF, UNIPHIER_SSCOLPQS);
  99
 100         do {
 101                 /* set cache operation */
 102                 writel(UNIPHIER_SSCOQM_CE | operation, UNIPHIER_SSCOQM);
 103
 104                 /* set address range if needed */
 105                 if (likely(UNIPHIER_SSCOQAD_IS_NEEDED(operation))) {
 106                         writel(start, UNIPHIER_SSCOQAD);
 107                         writel(size, UNIPHIER_SSCOQSZ);
 108                 }
 109
 110                 /* set target ways if needed */
 111                 if (unlikely(UNIPHIER_SSCOQWM_IS_NEEDED(operation)))
 112                         writel(ways, UNIPHIER_SSCOQWN);
 113         } while (unlikely(readl(UNIPHIER_SSCOPPQSEF) &
 114                           (UNIPHIER_SSCOPPQSEF_FE | UNIPHIER_SSCOPPQSEF_OE)));
 115
 116         /* wait until the operation is completed */
 117         while (likely(readl(UNIPHIER_SSCOLPQS) != UNIPHIER_SSCOLPQS_EF))
 118                 cpu_relax();
 119 }
 120
 121 static void uniphier_cache_maint_all(u32 operation)
 122 {
 123         uniphier_cache_maint_common(0, 0, 0, UNIPHIER_SSCOQM_S_ALL | operation);
 124
 125         uniphier_cache_sync();
 126 }
 127
 128 static void uniphier_cache_maint_range(u32 start, u32 end, u32 ways,
 129                                        u32 operation)
 130 {
 131         u32 size;
 132
 133         /*
 134          * If the start address is not aligned,
 135          * perform a cache operation for the first cache-line
 136          */
 137         start = start & ~(UNIPHIER_SSC_LINE_SIZE - 1);
 138
 139         size = end - start;
 140
 141         if (unlikely(size >= (u32)(-UNIPHIER_SSC_LINE_SIZE))) {
 142                 /* this means cache operation for all range */
 143                 uniphier_cache_maint_all(operation);
 144                 return;
 145         }
 146
 147         /*
 148          * If the end address is not aligned,
 149          * perform a cache operation for the last cache-line
 150          */
 151         size = ALIGN(size, UNIPHIER_SSC_LINE_SIZE);
 152
 153         while (size) {
 154                 u32 chunk_size = min_t(u32, size, UNIPHIER_SSC_RANGE_OP_MAX_SIZE);
 155
 156                 uniphier_cache_maint_common(start, chunk_size, ways,
 157                                             UNIPHIER_SSCOQM_S_RANGE | operation);
 158
 159                 start += chunk_size;
 160                 size -= chunk_size;
 161         }
 162
 163         uniphier_cache_sync();
 164 }
 165
 166 void uniphier_cache_prefetch_range(u32 start, u32 end, u32 ways)
 167 {
 168         uniphier_cache_maint_range(start, end, ways,
 169                                    UNIPHIER_SSCOQM_TID_WAY |
 170                                    UNIPHIER_SSCOQM_CM_PREFETCH);
 171 }
 172
 173 void uniphier_cache_touch_range(u32 start, u32 end, u32 ways)
 174 {
 175         uniphier_cache_maint_range(start, end, ways,
 176                                    UNIPHIER_SSCOQM_TID_WAY |
 177                                    UNIPHIER_SSCOQM_CM_TOUCH);
 178 }
 179
 180 void uniphier_cache_touch_zero_range(u32 start, u32 end, u32 ways)
 181 {
 182         uniphier_cache_maint_range(start, end, ways,
 183                                    UNIPHIER_SSCOQM_TID_WAY |
 184                                    UNIPHIER_SSCOQM_CM_TOUCH_ZERO);
 185 }
 186
 187 static void uniphier_cache_endisable(int enable)
 188 {
 189         u32 tmp;
 190
 191         tmp = readl(UNIPHIER_SSCC);
 192         if (enable)
 193                 tmp |= UNIPHIER_SSCC_ON;
 194         else
 195                 tmp &= ~UNIPHIER_SSCC_ON;
 196         writel(tmp, UNIPHIER_SSCC);
 197 }
 198
 199 void uniphier_cache_enable(void)
 200 {
 201         uniphier_cache_endisable(1);
 202 }
 203
 204 void uniphier_cache_disable(void)
 205 {
 206         uniphier_cache_endisable(0);
 207 }
 208
 209 #ifdef CONFIG_CACHE_UNIPHIER
 210 void v7_outer_cache_flush_all(void)
 211 {
 212         uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_FLUSH);
 213 }
 214
 215 void v7_outer_cache_inval_all(void)
 216 {
 217         uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_INV);
 218 }
 219
 220 void v7_outer_cache_flush_range(u32 start, u32 end)
 221 {
 222         uniphier_cache_maint_range(start, end, 0, UNIPHIER_SSCOQM_CM_FLUSH);
 223 }
 224
 225 void v7_outer_cache_inval_range(u32 start, u32 end)
 226 {
 227         if (start & (UNIPHIER_SSC_LINE_SIZE - 1)) {
 228                 start &= ~(UNIPHIER_SSC_LINE_SIZE - 1);
 229                 uniphier_cache_maint_range(start, UNIPHIER_SSC_LINE_SIZE, 0,
 230                                            UNIPHIER_SSCOQM_CM_FLUSH);
 231                 start += UNIPHIER_SSC_LINE_SIZE;
 232         }
 233
 234         if (start >= end) {
 235                 uniphier_cache_sync();
 236                 return;
 237         }
 238
 239         if (end & (UNIPHIER_SSC_LINE_SIZE - 1)) {
 240                 end &= ~(UNIPHIER_SSC_LINE_SIZE - 1);
 241                 uniphier_cache_maint_range(end, UNIPHIER_SSC_LINE_SIZE, 0,
 242                                            UNIPHIER_SSCOQM_CM_FLUSH);
 243         }
 244
 245         if (start >= end) {
 246                 uniphier_cache_sync();
 247                 return;
 248         }
 249
 250         uniphier_cache_maint_range(start, end, 0, UNIPHIER_SSCOQM_CM_INV);
 251 }
 252
 253 void v7_outer_cache_enable(void)
 254 {
 255         writel(U32_MAX, UNIPHIER_SSCLPDAWCR);   /* activate all ways */
 256         uniphier_cache_enable();
 257 }
 258
 259 void v7_outer_cache_disable(void)
 260 {
 261         uniphier_cache_disable();
 262 }
 263 #endif
 264
 265 void enable_caches(void)
 266 {
 267         dcache_enable();
 268 }