2 * Copyright (C) 2016 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/delay.h>
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
14 #include <linux/sizes.h>
19 #define SC_PLLCTRL_SSC_DK_MASK GENMASK(14, 0)
20 #define SC_PLLCTRL_SSC_EN BIT(31)
21 #define SC_PLLCTRL2_NRSTDS BIT(28)
22 #define SC_PLLCTRL2_SSC_JK_MASK GENMASK(26, 0)
23 #define SC_PLLCTRL3_REGI_MASK GENMASK(19, 16)
25 /* PLL type: VPLL27 */
26 #define SC_VPLL27CTRL_WP BIT(0)
27 #define SC_VPLL27CTRL3_K_LD BIT(28)
30 #define SC_DSPLLCTRL2_K_LD BIT(28)
32 int uniphier_ld20_sscpll_init(unsigned long reg_base
, unsigned int freq
,
33 unsigned int ssc_rate
, unsigned int divn
)
38 base
= ioremap(reg_base
, SZ_16
);
42 if (freq
!= UNIPHIER_PLL_FREQ_DEFAULT
) {
43 tmp
= readl(base
); /* SSCPLLCTRL */
44 tmp
&= ~SC_PLLCTRL_SSC_DK_MASK
;
45 tmp
|= FIELD_PREP(SC_PLLCTRL_SSC_DK_MASK
,
46 DIV_ROUND_CLOSEST(487UL * freq
* ssc_rate
,
50 tmp
= readl(base
+ 4);
51 tmp
&= ~SC_PLLCTRL2_SSC_JK_MASK
;
52 tmp
|= FIELD_PREP(SC_PLLCTRL2_SSC_JK_MASK
,
53 DIV_ROUND_CLOSEST(21431887UL * freq
,
55 writel(tmp
, base
+ 4);
60 tmp
= readl(base
+ 4); /* SSCPLLCTRL2 */
61 tmp
|= SC_PLLCTRL2_NRSTDS
;
62 writel(tmp
, base
+ 4);
69 int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base
)
74 base
= ioremap(reg_base
, SZ_16
);
78 tmp
= readl(base
); /* SSCPLLCTRL */
79 tmp
|= SC_PLLCTRL_SSC_EN
;
87 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base
, unsigned regi
)
92 base
= ioremap(reg_base
, SZ_16
);
96 tmp
= readl(base
+ 8); /* SSCPLLCTRL3 */
97 tmp
&= ~SC_PLLCTRL3_REGI_MASK
;
98 tmp
|= FIELD_PREP(SC_PLLCTRL3_REGI_MASK
, regi
);
99 writel(tmp
, base
+ 8);
106 int uniphier_ld20_vpll27_init(unsigned long reg_base
)
111 base
= ioremap(reg_base
, SZ_16
);
115 tmp
= readl(base
); /* VPLL27CTRL */
116 tmp
|= SC_VPLL27CTRL_WP
; /* write protect off */
119 tmp
= readl(base
+ 8); /* VPLL27CTRL3 */
120 tmp
|= SC_VPLL27CTRL3_K_LD
;
121 writel(tmp
, base
+ 8);
123 tmp
= readl(base
); /* VPLL27CTRL */
124 tmp
&= ~SC_VPLL27CTRL_WP
; /* write protect on */
132 int uniphier_ld20_dspll_init(unsigned long reg_base
)
137 base
= ioremap(reg_base
, SZ_16
);
141 tmp
= readl(base
+ 4); /* DSPLLCTRL2 */
142 tmp
|= SC_DSPLLCTRL2_K_LD
;
143 writel(tmp
, base
+ 4);