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git.ipfire.org Git - people/ms/u-boot.git/blob - arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
2 * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/sizes.h>
13 #include "ddrphy-regs.h"
23 static u32 umc_spcctla
[DRAM_SZ_NR
] = {0x002b0617, 0x003f0617, 0x00770617};
25 static void umc_start_ssif(void __iomem
*ssif_base
)
27 writel(0x00000000, ssif_base
+ 0x0000b004);
28 writel(0xffffffff, ssif_base
+ 0x0000c004);
29 writel(0x000fffcf, ssif_base
+ 0x0000c008);
30 writel(0x00000001, ssif_base
+ 0x0000b000);
31 writel(0x00000001, ssif_base
+ 0x0000c000);
33 writel(0x03010100, ssif_base
+ UMC_HDMCHSEL
);
34 writel(0x03010101, ssif_base
+ UMC_MDMCHSEL
);
35 writel(0x03010100, ssif_base
+ UMC_DVCCHSEL
);
36 writel(0x03010100, ssif_base
+ UMC_DMDCHSEL
);
38 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_FETCH
);
39 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_COMQUE0
);
40 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_COMWC0
);
41 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_COMRC0
);
42 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_COMQUE1
);
43 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_COMWC1
);
44 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_COMRC1
);
45 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_WC
);
46 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_RC
);
47 writel(0x00000000, ssif_base
+ UMC_CLKEN_SSIF_DST
);
48 writel(0x00000000, ssif_base
+ 0x0000c044); /* DCGIV_SSIF_REG */
50 writel(0x00000001, ssif_base
+ UMC_CPURST
);
51 writel(0x00000001, ssif_base
+ UMC_IDSRST
);
52 writel(0x00000001, ssif_base
+ UMC_IXMRST
);
53 writel(0x00000001, ssif_base
+ UMC_HDMRST
);
54 writel(0x00000001, ssif_base
+ UMC_MDMRST
);
55 writel(0x00000001, ssif_base
+ UMC_HDDRST
);
56 writel(0x00000001, ssif_base
+ UMC_MDDRST
);
57 writel(0x00000001, ssif_base
+ UMC_SIORST
);
58 writel(0x00000001, ssif_base
+ UMC_GIORST
);
59 writel(0x00000001, ssif_base
+ UMC_HD2RST
);
60 writel(0x00000001, ssif_base
+ UMC_VIORST
);
61 writel(0x00000001, ssif_base
+ UMC_DVCRST
);
62 writel(0x00000001, ssif_base
+ UMC_RGLRST
);
63 writel(0x00000001, ssif_base
+ UMC_VPERST
);
64 writel(0x00000001, ssif_base
+ UMC_AIORST
);
65 writel(0x00000001, ssif_base
+ UMC_DMDRST
);
68 static int umc_dramcont_init(void __iomem
*dramcont
, void __iomem
*ca_base
,
71 enum dram_size dram_size
;
73 switch (size
/ (width
/ 16)) {
75 dram_size
= DRAM_SZ_128M
;
78 dram_size
= DRAM_SZ_256M
;
81 dram_size
= DRAM_SZ_512M
;
84 pr_err("unsupported DRAM size\n");
88 writel(0x66bb0f17, dramcont
+ UMC_CMDCTLA
);
89 writel(0x18c6aa44, dramcont
+ UMC_CMDCTLB
);
90 writel(umc_spcctla
[dram_size
], dramcont
+ UMC_SPCCTLA
);
91 writel(0x00ff0008, dramcont
+ UMC_SPCCTLB
);
92 writel(0x000c00ae, dramcont
+ UMC_RDATACTL_D0
);
93 writel(0x000c00ae, dramcont
+ UMC_RDATACTL_D1
);
94 writel(0x04060802, dramcont
+ UMC_WDATACTL_D0
);
95 writel(0x04060802, dramcont
+ UMC_WDATACTL_D1
);
96 writel(0x04a02000, dramcont
+ UMC_DATASET
);
97 writel(0x00000000, ca_base
+ 0x2300);
98 writel(0x00400020, dramcont
+ UMC_DCCGCTL
);
99 writel(0x0000000f, dramcont
+ 0x7000);
100 writel(0x0000000f, dramcont
+ 0x8000);
101 writel(0x000000c3, dramcont
+ 0x8004);
102 writel(0x00000071, dramcont
+ 0x8008);
103 writel(0x00000004, dramcont
+ UMC_FLOWCTLG
);
104 writel(0x00000000, dramcont
+ 0x0060);
105 writel(0x80000201, ca_base
+ 0xc20);
106 writel(0x0801e01e, dramcont
+ UMC_FLOWCTLA
);
107 writel(0x00200000, dramcont
+ UMC_FLOWCTLB
);
108 writel(0x00004444, dramcont
+ UMC_FLOWCTLC
);
109 writel(0x200a0a00, dramcont
+ UMC_SPCSETB
);
110 writel(0x00010000, dramcont
+ UMC_SPCSETD
);
111 writel(0x80000020, dramcont
+ UMC_DFICUPDCTLA
);
116 int ph1_pro4_umc_init(const struct uniphier_board_data
*bd
)
118 void __iomem
*ssif_base
= (void __iomem
*)UMC_SSIF_BASE
;
119 void __iomem
*ca_base0
= (void __iomem
*)UMC_CA_BASE(0);
120 void __iomem
*ca_base1
= (void __iomem
*)UMC_CA_BASE(1);
121 void __iomem
*dramcont0
= (void __iomem
*)UMC_DRAMCONT_BASE(0);
122 void __iomem
*dramcont1
= (void __iomem
*)UMC_DRAMCONT_BASE(1);
123 void __iomem
*phy0_0
= (void __iomem
*)DDRPHY_BASE(0, 0);
124 void __iomem
*phy0_1
= (void __iomem
*)DDRPHY_BASE(0, 1);
125 void __iomem
*phy1_0
= (void __iomem
*)DDRPHY_BASE(1, 0);
126 void __iomem
*phy1_1
= (void __iomem
*)DDRPHY_BASE(1, 1);
129 if (bd
->dram_freq
!= 1600) {
130 pr_err("Unsupported DDR configuration\n");
134 umc_dram_init_start(dramcont0
);
135 umc_dram_init_start(dramcont1
);
136 umc_dram_init_poll(dramcont0
);
137 umc_dram_init_poll(dramcont1
);
139 writel(0x00000101, dramcont0
+ UMC_DIOCTLA
);
141 ph1_ld4_ddrphy_init(phy0_0
, bd
->dram_freq
, bd
->dram_ch
[0].size
,
144 ddrphy_prepare_training(phy0_0
, 0);
145 ddrphy_training(phy0_0
);
147 writel(0x00000103, dramcont0
+ UMC_DIOCTLA
);
149 ph1_ld4_ddrphy_init(phy0_1
, bd
->dram_freq
, bd
->dram_ch
[0].size
,
152 ddrphy_prepare_training(phy0_1
, 1);
153 ddrphy_training(phy0_1
);
155 writel(0x00000101, dramcont1
+ UMC_DIOCTLA
);
157 ph1_ld4_ddrphy_init(phy1_0
, bd
->dram_freq
, bd
->dram_ch
[1].size
,
160 ddrphy_prepare_training(phy1_0
, 0);
161 ddrphy_training(phy1_0
);
163 writel(0x00000103, dramcont1
+ UMC_DIOCTLA
);
165 ph1_ld4_ddrphy_init(phy1_1
, bd
->dram_freq
, bd
->dram_ch
[1].size
,
168 ddrphy_prepare_training(phy1_1
, 1);
169 ddrphy_training(phy1_1
);
171 ret
= umc_dramcont_init(dramcont0
, ca_base0
, bd
->dram_ch
[0].size
,
172 bd
->dram_ch
[0].width
);
176 ret
= umc_dramcont_init(dramcont1
, ca_base1
, bd
->dram_ch
[1].size
,
177 bd
->dram_ch
[1].width
);
181 umc_start_ssif(ssif_base
);