arch/arm/mach-uniphier/ph1-ld4/sbc_init.c

   1 /*
   2  * Copyright (C) 2011-2014 Panasonic Corporation
   3  *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/sbc-regs.h>
  11 #include <asm/arch/sg-regs.h>
  12
  13 void sbc_init(void)
  14 {
  15         u32 tmp;
  16
  17         /* system bus output enable */
  18         tmp = readl(PC0CTRL);
  19         tmp &= 0xfffffcff;
  20         writel(tmp, PC0CTRL);
  21
  22         /* XECS1: sub/boot memory (boot swap = off/on) */
  23         writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
  24         writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
  25         writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
  26         writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
  27
  28 #if !defined(CONFIG_SPL_BUILD)
  29         /* XECS0: boot/sub memory (boot swap = off/on) */
  30         writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
  31         writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
  32         writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
  33         writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
  34 #endif
  35         /* XECS3: peripherals */
  36         writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
  37         writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
  38         writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
  39         writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
  40
  41         /* base address regsiters */
  42         writel(0x0000bc01, SBBASE0);
  43         writel(0x0400bc01, SBBASE1);
  44         writel(0x0800bf01, SBBASE3);
  45
  46 #if !defined(CONFIG_SPL_BUILD)
  47         /* enable access to sub memory when boot swap is on */
  48         sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
  49 #endif
  50         sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
  51 }