arch/arm/mach-uniphier/sbc/sbc-ph1-ld4.c

   1 /*
   2  * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <linux/io.h>
   9 #include <mach/init.h>
  10 #include <mach/sbc-regs.h>
  11 #include <mach/sg-regs.h>
  12
  13 int ph1_ld4_sbc_init(const struct uniphier_board_data *bd)
  14 {
  15         u32 tmp;
  16
  17         /* system bus output enable */
  18         tmp = readl(PC0CTRL);
  19         tmp &= 0xfffffcff;
  20         writel(tmp, PC0CTRL);
  21
  22         /*
  23          * Only CS1 is connected to support card.
  24          * BKSZ[1:0] should be set to "01".
  25          */
  26         writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
  27         writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
  28         writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
  29         writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
  30
  31         if (boot_is_swapped()) {
  32                 /*
  33                  * Boot Swap On: boot from external NOR/SRAM
  34                  * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
  35                  *
  36                  * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
  37                  * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
  38                  */
  39                 writel(0x0000bc01, SBBASE0);
  40         } else {
  41                 /*
  42                  * Boot Swap Off: boot from mask ROM
  43                  * 0x40000000-0x41ffffff: mask ROM
  44                  * 0x42000000-0x43efffff: memory bank (31MB)
  45                  * 0x43f00000-0x43ffffff: peripherals (1MB)
  46                  */
  47                 writel(0x0000be01, SBBASE0); /* dummy */
  48                 writel(0x0200be01, SBBASE1);
  49         }
  50
  51         return 0;
  52 }