2 * Copyright (C) 2013 Soren Brinkmann <soren.brinkmann@xilinx.com>
3 * Copyright (C) 2013 Xilinx, Inc. All rights reserved.
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/hardware.h>
12 #include <asm/arch/clk.h>
14 /* Board oscillator frequency */
15 #ifndef CONFIG_ZYNQ_PS_CLK_FREQ
16 # define CONFIG_ZYNQ_PS_CLK_FREQ 33333333UL
19 /* Register bitfield defines */
20 #define PLLCTRL_FBDIV_MASK 0x7f000
21 #define PLLCTRL_FBDIV_SHIFT 12
22 #define PLLCTRL_BPFORCE_MASK (1 << 4)
23 #define PLLCTRL_PWRDWN_MASK 2
24 #define PLLCTRL_PWRDWN_SHIFT 1
25 #define PLLCTRL_RESET_MASK 1
26 #define PLLCTRL_RESET_SHIFT 0
28 #define ZYNQ_CLK_MAXDIV 0x3f
29 #define CLK_CTRL_DIV1_SHIFT 20
30 #define CLK_CTRL_DIV1_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
31 #define CLK_CTRL_DIV0_SHIFT 8
32 #define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
33 #define CLK_CTRL_SRCSEL_SHIFT 4
34 #define CLK_CTRL_SRCSEL_MASK (0x3 << CLK_CTRL_SRCSEL_SHIFT)
36 #define CLK_CTRL_DIV2X_SHIFT 26
37 #define CLK_CTRL_DIV2X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV2X_SHIFT)
38 #define CLK_CTRL_DIV3X_SHIFT 20
39 #define CLK_CTRL_DIV3X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV3X_SHIFT)
41 #define ZYNQ_CLKMUX_SEL_0 0
42 #define ZYNQ_CLKMUX_SEL_1 1
43 #define ZYNQ_CLKMUX_SEL_2 2
44 #define ZYNQ_CLKMUX_SEL_3 3
46 DECLARE_GLOBAL_DATA_PTR
;
51 * struct zynq_clk_ops:
52 * @set_rate: Function pointer to set_rate() implementation
53 * @get_rate: Function pointer to get_rate() implementation
56 int (*set_rate
)(struct clk
*clk
, unsigned long rate
);
57 unsigned long (*get_rate
)(struct clk
*clk
);
63 * @frequency: Currenct frequency
64 * @parent: Parent clock
66 * @reg: Clock control register
67 * @ops: Clock operations
71 unsigned long frequency
;
75 struct zynq_clk_ops ops
;
77 #define ZYNQ_CLK_FLAGS_HAS_2_DIVS 1
79 static struct clk clks
[clk_max
];
82 * __zynq_clk_cpu_get_parent() - Decode clock multiplexer
83 * @srcsel: Mux select value
84 * Returns the clock identifier associated with the selected mux input.
86 static int __zynq_clk_cpu_get_parent(unsigned int srcsel
)
91 case ZYNQ_CLKMUX_SEL_0
:
92 case ZYNQ_CLKMUX_SEL_1
:
95 case ZYNQ_CLKMUX_SEL_2
:
98 case ZYNQ_CLKMUX_SEL_3
:
110 * ddr2x_get_rate() - Get clock rate of DDR2x clock
112 * Returns the current clock rate of @clk.
114 static unsigned long ddr2x_get_rate(struct clk
*clk
)
116 u32 clk_ctrl
= readl(clk
->reg
);
117 u32 div
= (clk_ctrl
& CLK_CTRL_DIV2X_MASK
) >> CLK_CTRL_DIV2X_SHIFT
;
119 return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk
->parent
), div
);
123 * ddr3x_get_rate() - Get clock rate of DDR3x clock
125 * Returns the current clock rate of @clk.
127 static unsigned long ddr3x_get_rate(struct clk
*clk
)
129 u32 clk_ctrl
= readl(clk
->reg
);
130 u32 div
= (clk_ctrl
& CLK_CTRL_DIV3X_MASK
) >> CLK_CTRL_DIV3X_SHIFT
;
132 return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk
->parent
), div
);
135 static void init_ddr_clocks(void)
138 unsigned long prate
= zynq_clk_get_rate(ddrpll_clk
);
139 u32 clk_ctrl
= readl(&slcr_base
->ddr_clk_ctrl
);
142 clks
[ddr2x_clk
].reg
= &slcr_base
->ddr_clk_ctrl
;
143 clks
[ddr2x_clk
].parent
= ddrpll_clk
;
144 clks
[ddr2x_clk
].name
= "ddr_2x";
145 clks
[ddr2x_clk
].frequency
= ddr2x_get_rate(&clks
[ddr2x_clk
]);
146 clks
[ddr2x_clk
].ops
.get_rate
= ddr2x_get_rate
;
149 clks
[ddr3x_clk
].reg
= &slcr_base
->ddr_clk_ctrl
;
150 clks
[ddr3x_clk
].parent
= ddrpll_clk
;
151 clks
[ddr3x_clk
].name
= "ddr_3x";
152 clks
[ddr3x_clk
].frequency
= ddr3x_get_rate(&clks
[ddr3x_clk
]);
153 clks
[ddr3x_clk
].ops
.get_rate
= ddr3x_get_rate
;
156 clk_ctrl
= readl(&slcr_base
->dci_clk_ctrl
);
157 div0
= (clk_ctrl
& CLK_CTRL_DIV0_MASK
) >> CLK_CTRL_DIV0_SHIFT
;
158 div1
= (clk_ctrl
& CLK_CTRL_DIV1_MASK
) >> CLK_CTRL_DIV1_SHIFT
;
159 clks
[dci_clk
].reg
= &slcr_base
->dci_clk_ctrl
;
160 clks
[dci_clk
].parent
= ddrpll_clk
;
161 clks
[dci_clk
].frequency
= DIV_ROUND_CLOSEST(
162 DIV_ROUND_CLOSEST(prate
, div0
), div1
);
163 clks
[dci_clk
].name
= "dci";
165 gd
->bd
->bi_ddr_freq
= clks
[ddr3x_clk
].frequency
/ 1000000;
168 static void init_cpu_clocks(void)
171 u32 reg
, div
, srcsel
;
172 enum zynq_clk parent
;
174 reg
= readl(&slcr_base
->arm_clk_ctrl
);
175 clk_621
= readl(&slcr_base
->clk_621_true
) & 1;
176 div
= (reg
& CLK_CTRL_DIV0_MASK
) >> CLK_CTRL_DIV0_SHIFT
;
177 srcsel
= (reg
& CLK_CTRL_SRCSEL_MASK
) >> CLK_CTRL_SRCSEL_SHIFT
;
178 parent
= __zynq_clk_cpu_get_parent(srcsel
);
181 clks
[cpu_6or4x_clk
].reg
= &slcr_base
->arm_clk_ctrl
;
182 clks
[cpu_6or4x_clk
].parent
= parent
;
183 clks
[cpu_6or4x_clk
].frequency
= DIV_ROUND_CLOSEST(
184 zynq_clk_get_rate(parent
), div
);
185 clks
[cpu_6or4x_clk
].name
= "cpu_6or4x";
187 clks
[cpu_3or2x_clk
].reg
= &slcr_base
->arm_clk_ctrl
;
188 clks
[cpu_3or2x_clk
].parent
= cpu_6or4x_clk
;
189 clks
[cpu_3or2x_clk
].frequency
= zynq_clk_get_rate(cpu_6or4x_clk
) / 2;
190 clks
[cpu_3or2x_clk
].name
= "cpu_3or2x";
192 clks
[cpu_2x_clk
].reg
= &slcr_base
->arm_clk_ctrl
;
193 clks
[cpu_2x_clk
].parent
= cpu_6or4x_clk
;
194 clks
[cpu_2x_clk
].frequency
= zynq_clk_get_rate(cpu_6or4x_clk
) /
196 clks
[cpu_2x_clk
].name
= "cpu_2x";
198 clks
[cpu_1x_clk
].reg
= &slcr_base
->arm_clk_ctrl
;
199 clks
[cpu_1x_clk
].parent
= cpu_6or4x_clk
;
200 clks
[cpu_1x_clk
].frequency
= zynq_clk_get_rate(cpu_6or4x_clk
) /
202 clks
[cpu_1x_clk
].name
= "cpu_1x";
206 * periph_calc_two_divs() - Calculate clock dividers
207 * @cur_rate: Current clock rate
208 * @tgt_rate: Target clock rate
209 * @prate: Parent clock rate
210 * @div0: First divider (output)
211 * @div1: Second divider (output)
212 * Returns the actual clock rate possible.
214 * Calculates clock dividers for clocks with two 6-bit dividers.
216 static unsigned long periph_calc_two_divs(unsigned long cur_rate
,
217 unsigned long tgt_rate
, unsigned long prate
, u32
*div0
,
220 long err
, best_err
= (long)(~0UL >> 1);
221 unsigned long rate
, best_rate
= 0;
224 for (d0
= 1; d0
<= ZYNQ_CLK_MAXDIV
; d0
++) {
225 for (d1
= 1; d1
<= ZYNQ_CLK_MAXDIV
>> 1; d1
++) {
226 rate
= DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(prate
, d0
),
228 err
= abs(rate
- tgt_rate
);
230 if (err
< best_err
) {
243 * zynq_clk_periph_set_rate() - Set clock rate
244 * @clk: Handle of the peripheral clock
245 * @rate: New clock rate
246 * Sets the clock frequency of @clk to @rate. Returns zero on success.
248 static int zynq_clk_periph_set_rate(struct clk
*clk
,
251 u32 ctrl
, div0
= 0, div1
= 0;
252 unsigned long prate
, new_rate
, cur_rate
= clk
->frequency
;
254 ctrl
= readl(clk
->reg
);
255 prate
= zynq_clk_get_rate(clk
->parent
);
256 ctrl
&= ~CLK_CTRL_DIV0_MASK
;
258 if (clk
->flags
& ZYNQ_CLK_FLAGS_HAS_2_DIVS
) {
259 ctrl
&= ~CLK_CTRL_DIV1_MASK
;
260 new_rate
= periph_calc_two_divs(cur_rate
, rate
, prate
, &div0
,
262 ctrl
|= div1
<< CLK_CTRL_DIV1_SHIFT
;
264 div0
= DIV_ROUND_CLOSEST(prate
, rate
);
265 div0
&= ZYNQ_CLK_MAXDIV
;
266 new_rate
= DIV_ROUND_CLOSEST(rate
, div0
);
269 /* write new divs to hardware */
270 ctrl
|= div0
<< CLK_CTRL_DIV0_SHIFT
;
271 writel(ctrl
, clk
->reg
);
273 /* update frequency in clk framework */
274 clk
->frequency
= new_rate
;
280 * zynq_clk_periph_get_rate() - Get clock rate
281 * @clk: Handle of the peripheral clock
282 * Returns the current clock rate of @clk.
284 static unsigned long zynq_clk_periph_get_rate(struct clk
*clk
)
286 u32 clk_ctrl
= readl(clk
->reg
);
287 u32 div0
= (clk_ctrl
& CLK_CTRL_DIV0_MASK
) >> CLK_CTRL_DIV0_SHIFT
;
290 if (clk
->flags
& ZYNQ_CLK_FLAGS_HAS_2_DIVS
)
291 div1
= (clk_ctrl
& CLK_CTRL_DIV1_MASK
) >> CLK_CTRL_DIV1_SHIFT
;
293 /* a register value of zero == division by 1 */
301 DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk
->parent
), div0
),
306 * __zynq_clk_periph_get_parent() - Decode clock multiplexer
307 * @srcsel: Mux select value
308 * Returns the clock identifier associated with the selected mux input.
310 static enum zynq_clk
__zynq_clk_periph_get_parent(u32 srcsel
)
313 case ZYNQ_CLKMUX_SEL_0
:
314 case ZYNQ_CLKMUX_SEL_1
:
316 case ZYNQ_CLKMUX_SEL_2
:
318 case ZYNQ_CLKMUX_SEL_3
:
326 * zynq_clk_periph_get_parent() - Decode clock multiplexer
328 * Returns the clock identifier associated with the selected mux input.
330 static enum zynq_clk
zynq_clk_periph_get_parent(struct clk
*clk
)
332 u32 clk_ctrl
= readl(clk
->reg
);
333 u32 srcsel
= (clk_ctrl
& CLK_CTRL_SRCSEL_MASK
) >> CLK_CTRL_SRCSEL_SHIFT
;
335 return __zynq_clk_periph_get_parent(srcsel
);
339 * zynq_clk_register_periph_clk() - Set up a peripheral clock with the framework
340 * @clk: Pointer to struct clk for the clock
341 * @ctrl: Clock control register
343 * @two_divs: Indicates whether the clock features one or two dividers
345 static int zynq_clk_register_periph_clk(struct clk
*clk
, u32
*ctrl
, char *name
,
351 clk
->flags
= ZYNQ_CLK_FLAGS_HAS_2_DIVS
;
352 clk
->parent
= zynq_clk_periph_get_parent(clk
);
353 clk
->frequency
= zynq_clk_periph_get_rate(clk
);
354 clk
->ops
.get_rate
= zynq_clk_periph_get_rate
;
355 clk
->ops
.set_rate
= zynq_clk_periph_set_rate
;
360 static void init_periph_clocks(void)
362 zynq_clk_register_periph_clk(&clks
[gem0_clk
], &slcr_base
->gem0_clk_ctrl
,
364 zynq_clk_register_periph_clk(&clks
[gem1_clk
], &slcr_base
->gem1_clk_ctrl
,
367 zynq_clk_register_periph_clk(&clks
[smc_clk
], &slcr_base
->smc_clk_ctrl
,
370 zynq_clk_register_periph_clk(&clks
[lqspi_clk
],
371 &slcr_base
->lqspi_clk_ctrl
, "lqspi", 0);
373 zynq_clk_register_periph_clk(&clks
[sdio0_clk
],
374 &slcr_base
->sdio_clk_ctrl
, "sdio0", 0);
375 zynq_clk_register_periph_clk(&clks
[sdio1_clk
],
376 &slcr_base
->sdio_clk_ctrl
, "sdio1", 0);
378 zynq_clk_register_periph_clk(&clks
[spi0_clk
], &slcr_base
->spi_clk_ctrl
,
380 zynq_clk_register_periph_clk(&clks
[spi1_clk
], &slcr_base
->spi_clk_ctrl
,
383 zynq_clk_register_periph_clk(&clks
[uart0_clk
],
384 &slcr_base
->uart_clk_ctrl
, "uart0", 0);
385 zynq_clk_register_periph_clk(&clks
[uart1_clk
],
386 &slcr_base
->uart_clk_ctrl
, "uart1", 0);
388 zynq_clk_register_periph_clk(&clks
[dbg_trc_clk
],
389 &slcr_base
->dbg_clk_ctrl
, "dbg_trc", 0);
390 zynq_clk_register_periph_clk(&clks
[dbg_apb_clk
],
391 &slcr_base
->dbg_clk_ctrl
, "dbg_apb", 0);
393 zynq_clk_register_periph_clk(&clks
[pcap_clk
],
394 &slcr_base
->pcap_clk_ctrl
, "pcap", 0);
396 zynq_clk_register_periph_clk(&clks
[fclk0_clk
],
397 &slcr_base
->fpga0_clk_ctrl
, "fclk0", 1);
398 zynq_clk_register_periph_clk(&clks
[fclk1_clk
],
399 &slcr_base
->fpga1_clk_ctrl
, "fclk1", 1);
400 zynq_clk_register_periph_clk(&clks
[fclk2_clk
],
401 &slcr_base
->fpga2_clk_ctrl
, "fclk2", 1);
402 zynq_clk_register_periph_clk(&clks
[fclk3_clk
],
403 &slcr_base
->fpga3_clk_ctrl
, "fclk3", 1);
407 * zynq_clk_register_aper_clk() - Set up a APER clock with the framework
408 * @clk: Pointer to struct clk for the clock
409 * @ctrl: Clock control register
412 static void zynq_clk_register_aper_clk(struct clk
*clk
, u32
*ctrl
, char *name
)
416 clk
->parent
= cpu_1x_clk
;
417 clk
->frequency
= zynq_clk_get_rate(clk
->parent
);
420 static void init_aper_clocks(void)
422 zynq_clk_register_aper_clk(&clks
[usb0_aper_clk
],
423 &slcr_base
->aper_clk_ctrl
, "usb0_aper");
424 zynq_clk_register_aper_clk(&clks
[usb1_aper_clk
],
425 &slcr_base
->aper_clk_ctrl
, "usb1_aper");
427 zynq_clk_register_aper_clk(&clks
[gem0_aper_clk
],
428 &slcr_base
->aper_clk_ctrl
, "gem0_aper");
429 zynq_clk_register_aper_clk(&clks
[gem1_aper_clk
],
430 &slcr_base
->aper_clk_ctrl
, "gem1_aper");
432 zynq_clk_register_aper_clk(&clks
[sdio0_aper_clk
],
433 &slcr_base
->aper_clk_ctrl
, "sdio0_aper");
434 zynq_clk_register_aper_clk(&clks
[sdio1_aper_clk
],
435 &slcr_base
->aper_clk_ctrl
, "sdio1_aper");
437 zynq_clk_register_aper_clk(&clks
[spi0_aper_clk
],
438 &slcr_base
->aper_clk_ctrl
, "spi0_aper");
439 zynq_clk_register_aper_clk(&clks
[spi1_aper_clk
],
440 &slcr_base
->aper_clk_ctrl
, "spi1_aper");
442 zynq_clk_register_aper_clk(&clks
[can0_aper_clk
],
443 &slcr_base
->aper_clk_ctrl
, "can0_aper");
444 zynq_clk_register_aper_clk(&clks
[can1_aper_clk
],
445 &slcr_base
->aper_clk_ctrl
, "can1_aper");
447 zynq_clk_register_aper_clk(&clks
[i2c0_aper_clk
],
448 &slcr_base
->aper_clk_ctrl
, "i2c0_aper");
449 zynq_clk_register_aper_clk(&clks
[i2c1_aper_clk
],
450 &slcr_base
->aper_clk_ctrl
, "i2c1_aper");
452 zynq_clk_register_aper_clk(&clks
[uart0_aper_clk
],
453 &slcr_base
->aper_clk_ctrl
, "uart0_aper");
454 zynq_clk_register_aper_clk(&clks
[uart1_aper_clk
],
455 &slcr_base
->aper_clk_ctrl
, "uart1_aper");
457 zynq_clk_register_aper_clk(&clks
[gpio_aper_clk
],
458 &slcr_base
->aper_clk_ctrl
, "gpio_aper");
460 zynq_clk_register_aper_clk(&clks
[lqspi_aper_clk
],
461 &slcr_base
->aper_clk_ctrl
, "lqspi_aper");
463 zynq_clk_register_aper_clk(&clks
[smc_aper_clk
],
464 &slcr_base
->aper_clk_ctrl
, "smc_aper");
468 * __zynq_clk_pll_get_rate() - Get PLL rate
469 * @addr: Address of the PLL's control register
470 * Returns the current PLL output rate.
472 static unsigned long __zynq_clk_pll_get_rate(u32
*addr
)
474 u32 reg
, mul
, bypass
;
477 bypass
= reg
& PLLCTRL_BPFORCE_MASK
;
481 mul
= (reg
& PLLCTRL_FBDIV_MASK
) >> PLLCTRL_FBDIV_SHIFT
;
483 return CONFIG_ZYNQ_PS_CLK_FREQ
* mul
;
487 * zynq_clk_pll_get_rate() - Get PLL rate
488 * @pll: Handle of the PLL
489 * Returns the current clock rate of @pll.
491 static unsigned long zynq_clk_pll_get_rate(struct clk
*pll
)
493 return __zynq_clk_pll_get_rate(pll
->reg
);
497 * zynq_clk_register_pll() - Set up a PLL with the framework
498 * @clk: Pointer to struct clk for the PLL
499 * @ctrl: PLL control register
501 * @prate: PLL input clock rate
503 static void zynq_clk_register_pll(struct clk
*clk
, u32
*ctrl
, char *name
,
508 clk
->frequency
= zynq_clk_pll_get_rate(clk
);
509 clk
->ops
.get_rate
= zynq_clk_pll_get_rate
;
513 * clkid_2_register() - Get clock control register
514 * @id: Clock identifier of one of the PLLs
515 * Returns the address of the requested PLL's control register.
517 static u32
*clkid_2_register(enum zynq_clk id
)
521 return &slcr_base
->arm_pll_ctrl
;
523 return &slcr_base
->ddr_pll_ctrl
;
525 return &slcr_base
->io_pll_ctrl
;
527 return &slcr_base
->io_pll_ctrl
;
533 * zynq_clk_early_init() - Early init for the clock framework
535 * This function is called from before relocation and sets up the CPU clock
536 * frequency in the global data struct.
538 void zynq_clk_early_init(void)
540 u32 reg
= readl(&slcr_base
->arm_clk_ctrl
);
541 u32 div
= (reg
& CLK_CTRL_DIV0_MASK
) >> CLK_CTRL_DIV0_SHIFT
;
542 u32 srcsel
= (reg
& CLK_CTRL_SRCSEL_MASK
) >> CLK_CTRL_SRCSEL_SHIFT
;
543 enum zynq_clk parent
= __zynq_clk_cpu_get_parent(srcsel
);
544 u32
*pllreg
= clkid_2_register(parent
);
545 unsigned long prate
= __zynq_clk_pll_get_rate(pllreg
);
550 gd
->cpu_clk
= DIV_ROUND_CLOSEST(prate
, div
);
554 * get_uart_clk() - Get UART input frequency
555 * @dev_index: UART ID
556 * Returns UART input clock frequency in Hz.
558 * Compared to zynq_clk_get_rate() this function is designed to work before
559 * relocation and can be called when the serial UART is set up.
561 unsigned long get_uart_clk(int dev_index
)
563 u32 reg
= readl(&slcr_base
->uart_clk_ctrl
);
564 u32 div
= (reg
& CLK_CTRL_DIV0_MASK
) >> CLK_CTRL_DIV0_SHIFT
;
565 u32 srcsel
= (reg
& CLK_CTRL_SRCSEL_MASK
) >> CLK_CTRL_SRCSEL_SHIFT
;
566 enum zynq_clk parent
= __zynq_clk_periph_get_parent(srcsel
);
567 u32
*pllreg
= clkid_2_register(parent
);
568 unsigned long prate
= __zynq_clk_pll_get_rate(pllreg
);
573 return DIV_ROUND_CLOSEST(prate
, div
);
577 * set_cpu_clk_info() - Initialize clock framework
578 * Always returns zero.
580 * This function is called from common code after relocation and sets up the
581 * clock framework. The framework must not be used before this function had been
584 int set_cpu_clk_info(void)
586 zynq_clk_register_pll(&clks
[armpll_clk
], &slcr_base
->arm_pll_ctrl
,
587 "armpll", CONFIG_ZYNQ_PS_CLK_FREQ
);
588 zynq_clk_register_pll(&clks
[ddrpll_clk
], &slcr_base
->ddr_pll_ctrl
,
589 "ddrpll", CONFIG_ZYNQ_PS_CLK_FREQ
);
590 zynq_clk_register_pll(&clks
[iopll_clk
], &slcr_base
->io_pll_ctrl
,
591 "iopll", CONFIG_ZYNQ_PS_CLK_FREQ
);
595 init_periph_clocks();
598 gd
->bd
->bi_arm_freq
= gd
->cpu_clk
/ 1000000;
599 gd
->bd
->bi_dsp_freq
= 0;
605 * zynq_clk_get_rate() - Get clock rate
606 * @clk: Clock identifier
607 * Returns the current clock rate of @clk on success or zero for an invalid
610 unsigned long zynq_clk_get_rate(enum zynq_clk clk
)
612 if (clk
< 0 || clk
>= clk_max
)
615 return clks
[clk
].frequency
;
619 * zynq_clk_set_rate() - Set clock rate
620 * @clk: Clock identifier
621 * @rate: Requested clock rate
622 * Passes on the return value from the clock's set_rate() function or negative
625 int zynq_clk_set_rate(enum zynq_clk clk
, unsigned long rate
)
627 if (clk
< 0 || clk
>= clk_max
)
630 if (clks
[clk
].ops
.set_rate
)
631 return clks
[clk
].ops
.set_rate(&clks
[clk
], rate
);
637 * zynq_clk_get_name() - Get clock name
638 * @clk: Clock identifier
639 * Returns the name of @clk.
641 const char *zynq_clk_get_name(enum zynq_clk clk
)
643 return clks
[clk
].name
;
647 * soc_clk_dump() - Print clock frequencies
648 * Returns zero on success
650 * Implementation for the clk dump command.
652 int soc_clk_dump(void)
656 printf("clk\t\tfrequency\n");
657 for (i
= 0; i
< clk_max
; i
++) {
658 const char *name
= zynq_clk_get_name(i
);
660 printf("%10s%20lu\n", name
, zynq_clk_get_rate(i
));