arch/arm/mach-zynq/include/mach/clk.h

   1 /*
   2  * Copyright (c) 2013 Xilinx Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _ZYNQ_CLK_H_
   8 #define _ZYNQ_CLK_H_
   9
  10 enum zynq_clk {
  11         armpll_clk, ddrpll_clk, iopll_clk,
  12         cpu_6or4x_clk, cpu_3or2x_clk, cpu_2x_clk, cpu_1x_clk,
  13         ddr2x_clk, ddr3x_clk, dci_clk,
  14         lqspi_clk, smc_clk, pcap_clk, gem0_clk, gem1_clk,
  15         fclk0_clk, fclk1_clk, fclk2_clk, fclk3_clk, can0_clk, can1_clk,
  16         sdio0_clk, sdio1_clk, uart0_clk, uart1_clk, spi0_clk, spi1_clk, dma_clk,
  17         usb0_aper_clk, usb1_aper_clk, gem0_aper_clk, gem1_aper_clk,
  18         sdio0_aper_clk, sdio1_aper_clk, spi0_aper_clk, spi1_aper_clk,
  19         can0_aper_clk, can1_aper_clk, i2c0_aper_clk, i2c1_aper_clk,
  20         uart0_aper_clk, uart1_aper_clk, gpio_aper_clk, lqspi_aper_clk,
  21         smc_aper_clk, swdt_clk, dbg_trc_clk, dbg_apb_clk, clk_max};
  22
  23 void zynq_clk_early_init(void);
  24 int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate);
  25 unsigned long zynq_clk_get_rate(enum zynq_clk clk);
  26 const char *zynq_clk_get_name(enum zynq_clk clk);
  27 unsigned long get_uart_clk(int dev_id);
  28
  29 #endif