arch/avr32/cpu/hsdramc.c

   1 /*
   2  * Copyright (C) 2005-2006 Atmel Corporation
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7
   8 #include <asm/io.h>
   9 #include <asm/sdram.h>
  10
  11 #include <asm/arch/clk.h>
  12 #include <asm/arch/hardware.h>
  13
  14 #include "hsdramc1.h"
  15
  16 unsigned long sdram_init(void *sdram_base, const struct sdram_config *config)
  17 {
  18         unsigned long sdram_size;
  19         uint32_t cfgreg;
  20         unsigned int i;
  21
  22         cfgreg = (HSDRAMC1_BF(NC, config->col_bits - 8)
  23                        | HSDRAMC1_BF(NR, config->row_bits - 11)
  24                        | HSDRAMC1_BF(NB, config->bank_bits - 1)
  25                        | HSDRAMC1_BF(CAS, config->cas)
  26                        | HSDRAMC1_BF(TWR, config->twr)
  27                        | HSDRAMC1_BF(TRC, config->trc)
  28                        | HSDRAMC1_BF(TRP, config->trp)
  29                        | HSDRAMC1_BF(TRCD, config->trcd)
  30                        | HSDRAMC1_BF(TRAS, config->tras)
  31                        | HSDRAMC1_BF(TXSR, config->txsr));
  32
  33         if (config->data_bits == SDRAM_DATA_16BIT)
  34                 cfgreg |= HSDRAMC1_BIT(DBW);
  35
  36         hsdramc1_writel(CR, cfgreg);
  37
  38         /* Send a NOP to turn on the clock (necessary on some chips) */
  39         hsdramc1_writel(MR, HSDRAMC1_MODE_NOP);
  40         hsdramc1_readl(MR);
  41         writel(0, sdram_base);
  42
  43         /*
  44          * Initialization sequence for SDRAM, from the data sheet:
  45          *
  46          * 1. A minimum pause of 200 us is provided to precede any
  47          *    signal toggle.
  48          */
  49         udelay(200);
  50
  51         /*
  52          * 2. A Precharge All command is issued to the SDRAM
  53          */
  54         hsdramc1_writel(MR, HSDRAMC1_MODE_BANKS_PRECHARGE);
  55         hsdramc1_readl(MR);
  56         writel(0, sdram_base);
  57
  58         /*
  59          * 3. Eight auto-refresh (CBR) cycles are provided
  60          */
  61         hsdramc1_writel(MR, HSDRAMC1_MODE_AUTO_REFRESH);
  62         hsdramc1_readl(MR);
  63         for (i = 0; i < 8; i++)
  64                 writel(0, sdram_base);
  65
  66         /*
  67          * 4. A mode register set (MRS) cycle is issued to program
  68          *    SDRAM parameters, in particular CAS latency and burst
  69          *    length.
  70          *
  71          * The address will be chosen by the SDRAMC automatically; we
  72          * just have to make sure BA[1:0] are set to 0.
  73          */
  74         hsdramc1_writel(MR, HSDRAMC1_MODE_LOAD_MODE);
  75         hsdramc1_readl(MR);
  76         writel(0, sdram_base);
  77
  78         /*
  79          * 5. The application must go into Normal Mode, setting Mode
  80          *    to 0 in the Mode Register and performing a write access
  81          *    at any location in the SDRAM.
  82          */
  83         hsdramc1_writel(MR, HSDRAMC1_MODE_NORMAL);
  84         hsdramc1_readl(MR);
  85         writel(0, sdram_base);
  86
  87         /*
  88          * 6. Write refresh rate into SDRAMC refresh timer count
  89          *    register (refresh rate = timing between refresh cycles).
  90          */
  91         hsdramc1_writel(TR, config->refresh_period);
  92
  93         if (config->data_bits == SDRAM_DATA_16BIT)
  94                 sdram_size = 1 << (config->row_bits + config->col_bits
  95                                    + config->bank_bits + 1);
  96         else
  97                 sdram_size = 1 << (config->row_bits + config->col_bits
  98                                    + config->bank_bits + 2);
  99
 100         return sdram_size;
 101 }