arch/blackfin/include/asm/mach-bf506/anomaly.h

   1 /*
   2  * DO NOT EDIT THIS FILE
   3  * This file is under version control at
   4  *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
   5  * and can be replaced with that version at any time
   6  * DO NOT EDIT THIS FILE
   7  *
   8  * Copyright 2004-2010 Analog Devices Inc.
   9  * Licensed under the ADI BSD license.
  10  *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
  11  */
  12
  13 /* This file should be up to date with:
  14  */
  15
  16 #if __SILICON_REVISION__ < 0
  17 # error will not work on BF506 silicon version
  18 #endif
  19
  20 #ifndef _MACH_ANOMALY_H_
  21 #define _MACH_ANOMALY_H_
  22
  23 /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
  24 #define ANOMALY_05000074 (1)
  25 /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
  26 #define ANOMALY_05000119 (1)
  27 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
  28 #define ANOMALY_05000122 (1)
  29 /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
  30 #define ANOMALY_05000245 (1)
  31 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
  32 #define ANOMALY_05000254 (1)
  33 /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
  34 #define ANOMALY_05000265 (1)
  35 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
  36 #define ANOMALY_05000310 (1)
  37 /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
  38 #define ANOMALY_05000366 (1)
  39 /* Speculative Fetches Can Cause Undesired External FIFO Operations */
  40 #define ANOMALY_05000416 (1)
  41 /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
  42 #define ANOMALY_05000426 (1)
  43 /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
  44 #define ANOMALY_05000443 (1)
  45 /* UART IrDA Receiver Fails on Extended Bit Pulses */
  46 #define ANOMALY_05000447 (1)
  47 /* False Hardware Error when RETI Points to Invalid Memory */
  48 #define ANOMALY_05000461 (1)
  49 /* PLL Latches Incorrect Settings During Reset */
  50 #define ANOMALY_05000469 (1)
  51 /* Incorrect Default MSEL Value in PLL_CTL */
  52 #define ANOMALY_05000472 (1)
  53 /* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
  54 #define ANOMALY_05000473 (1)
  55 /* TESTSET Instruction Cannot Be Interrupted */
  56 #define ANOMALY_05000477 (1)
  57 /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
  58 #define ANOMALY_05000481 (1)
  59 /* IFLUSH sucks at life */
  60 #define ANOMALY_05000491 (1)
  61
  62 /* Anomalies that don't exist on this proc */
  63 #define ANOMALY_05000099 (0)
  64 #define ANOMALY_05000120 (0)
  65 #define ANOMALY_05000125 (0)
  66 #define ANOMALY_05000149 (0)
  67 #define ANOMALY_05000158 (0)
  68 #define ANOMALY_05000171 (0)
  69 #define ANOMALY_05000179 (0)
  70 #define ANOMALY_05000182 (0)
  71 #define ANOMALY_05000183 (0)
  72 #define ANOMALY_05000189 (0)
  73 #define ANOMALY_05000198 (0)
  74 #define ANOMALY_05000202 (0)
  75 #define ANOMALY_05000215 (0)
  76 #define ANOMALY_05000219 (0)
  77 #define ANOMALY_05000220 (0)
  78 #define ANOMALY_05000227 (0)
  79 #define ANOMALY_05000230 (0)
  80 #define ANOMALY_05000231 (0)
  81 #define ANOMALY_05000233 (0)
  82 #define ANOMALY_05000234 (0)
  83 #define ANOMALY_05000242 (0)
  84 #define ANOMALY_05000244 (0)
  85 #define ANOMALY_05000248 (0)
  86 #define ANOMALY_05000250 (0)
  87 #define ANOMALY_05000257 (0)
  88 #define ANOMALY_05000261 (0)
  89 #define ANOMALY_05000263 (0)
  90 #define ANOMALY_05000266 (0)
  91 #define ANOMALY_05000273 (0)
  92 #define ANOMALY_05000274 (0)
  93 #define ANOMALY_05000278 (0)
  94 #define ANOMALY_05000281 (0)
  95 #define ANOMALY_05000283 (0)
  96 #define ANOMALY_05000285 (0)
  97 #define ANOMALY_05000287 (0)
  98 #define ANOMALY_05000301 (0)
  99 #define ANOMALY_05000305 (0)
 100 #define ANOMALY_05000307 (0)
 101 #define ANOMALY_05000311 (0)
 102 #define ANOMALY_05000312 (0)
 103 #define ANOMALY_05000315 (0)
 104 #define ANOMALY_05000323 (0)
 105 #define ANOMALY_05000353 (0)
 106 #define ANOMALY_05000357 (0)
 107 #define ANOMALY_05000362 (1)
 108 #define ANOMALY_05000363 (0)
 109 #define ANOMALY_05000364 (0)
 110 #define ANOMALY_05000371 (0)
 111 #define ANOMALY_05000380 (0)
 112 #define ANOMALY_05000386 (0)
 113 #define ANOMALY_05000389 (0)
 114 #define ANOMALY_05000400 (0)
 115 #define ANOMALY_05000402 (0)
 116 #define ANOMALY_05000412 (0)
 117 #define ANOMALY_05000432 (0)
 118 #define ANOMALY_05000440 (0)
 119 #define ANOMALY_05000448 (0)
 120 #define ANOMALY_05000456 (0)
 121 #define ANOMALY_05000450 (0)
 122 #define ANOMALY_05000465 (0)
 123 #define ANOMALY_05000467 (0)
 124 #define ANOMALY_05000474 (0)
 125 #define ANOMALY_05000475 (0)
 126 #define ANOMALY_05000485 (0)
 127
 128 #endif