arch/blackfin/include/asm/mach-bf527/portmux.h

   1 /*
   2  * Copyright 2007-2009 Analog Devices Inc.
   3  *
   4  * Licensed under the GPL-2 or later
   5  */
   6
   7 #ifndef _MACH_PORTMUX_H_
   8 #define _MACH_PORTMUX_H_
   9
  10 #define MAX_RESOURCES   MAX_BLACKFIN_GPIOS
  11
  12 #define P_PPI0_D0       (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
  13 #define P_PPI0_D1       (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
  14 #define P_PPI0_D2       (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
  15 #define P_PPI0_D3       (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
  16 #define P_PPI0_D4       (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
  17 #define P_PPI0_D5       (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
  18 #define P_PPI0_D6       (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
  19 #define P_PPI0_D7       (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
  20 #define P_PPI0_D8       (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
  21 #define P_PPI0_D9       (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
  22 #define P_PPI0_D10      (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
  23 #define P_PPI0_D11      (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
  24 #define P_PPI0_D12      (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
  25 #define P_PPI0_D13      (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
  26 #define P_PPI0_D14      (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
  27 #define P_PPI0_D15      (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
  28
  29 #if !defined(CONFIG_BF527_SPORT0_PORTG)
  30 #define P_SPORT0_DRPRI  (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
  31 #define P_SPORT0_RFS    (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
  32 #define P_SPORT0_RSCLK  (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
  33 #define P_SPORT0_DTPRI  (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
  34 #define P_SPORT0_TFS    (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
  35 #define P_SPORT0_TSCLK  (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
  36 #define P_SPORT0_DTSEC  (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
  37 #define P_SPORT0_DRSEC  (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
  38 #else
  39 #define P_SPORT0_DTPRI  (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
  40 #define P_SPORT0_DRSEC  (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
  41 #define P_SPORT0_DTSEC  (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
  42 #define P_SPORT0_DRPRI  (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
  43 #define P_SPORT0_RFS    (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
  44 #define P_SPORT0_RSCLK  (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
  45 #if !defined(CONFIG_BF527_SPORT0_TSCLK_PG14)
  46 #define P_SPORT0_TSCLK  (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
  47 #else
  48 #define P_SPORT0_TSCLK  (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
  49 #endif
  50 #define P_SPORT0_TFS    (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
  51 #endif
  52
  53 #define P_SPORT1_DRPRI  (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
  54 #define P_SPORT1_RSCLK  (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
  55 #define P_SPORT1_RFS    (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
  56 #define P_SPORT1_TFS    (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
  57 #define P_SPORT1_DTPRI  (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
  58 #define P_SPORT1_TSCLK  (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
  59 #define P_SPORT1_DTSEC  (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
  60 #define P_SPORT1_DRSEC  (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
  61
  62 #define P_SPI0_SSEL6    (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
  63 #define P_SPI0_SSEL7    (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
  64
  65 #define P_SPI0_SSEL2    (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
  66 #define P_SPI0_SSEL3    (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
  67
  68 #if !defined(CONFIG_BF527_UART1_PORTG)
  69 #define P_UART1_TX      (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
  70 #define P_UART1_RX      (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
  71 #else
  72 #define P_UART1_TX      (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
  73 #define P_UART1_RX      (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
  74 #endif
  75
  76 #define P_CNT_CZM       (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(3))
  77 #define P_CNT_CDG       (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(3))
  78 #define P_CNT_CUD       (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(3))
  79
  80 #define P_HWAIT         (P_DONTCARE)
  81
  82 #define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG1
  83 #define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
  84
  85 #define P_SPI0_SS       (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
  86 #define P_SPI0_SSEL1    (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
  87 #define P_SPI0_SCK      (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
  88 #define P_SPI0_MISO     (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
  89 #define P_SPI0_MOSI     (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
  90 #define P_TMR1          (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
  91 #define P_PPI0_FS2      (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
  92 #define P_TMR3          (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
  93 #define P_TMR4          (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
  94 #define P_TMR5          (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
  95 #define P_TMR6          (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
  96 /* #define P_TMR7               (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) */
  97 #define P_DMAR1         (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
  98 #define P_DMAR0         (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
  99 #define P_TMR2          (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
 100 #define P_TMR7          (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
 101 #define P_MDC           (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
 102 #define P_RMII0_MDINT   (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
 103 #define P_MII0_PHYINT   (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
 104
 105 #define P_PPI0_FS3      (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
 106 #define P_UART0_TX      (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
 107 #define P_UART0_RX      (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
 108
 109 #define P_HOST_WR       (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
 110 #define P_HOST_ACK      (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
 111 #define P_HOST_ADDR     (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
 112 #define P_HOST_RD       (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
 113 #define P_HOST_CE       (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
 114
 115 #if defined(CONFIG_BF527_NAND_D_PORTF)
 116 #define P_NAND_D0       (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
 117 #define P_NAND_D1       (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
 118 #define P_NAND_D2       (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
 119 #define P_NAND_D3       (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
 120 #define P_NAND_D4       (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
 121 #define P_NAND_D5       (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
 122 #define P_NAND_D6       (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
 123 #define P_NAND_D7       (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
 124 #else /*if defined(CONFIG_BF527_NAND_D_PORTH)*/
 125 #define P_NAND_D0       (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
 126 #define P_NAND_D1       (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
 127 #define P_NAND_D2       (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
 128 #define P_NAND_D3       (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
 129 #define P_NAND_D4       (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
 130 #define P_NAND_D5       (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
 131 #define P_NAND_D6       (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
 132 #define P_NAND_D7       (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
 133 #endif
 134
 135 #define P_SPI0_SSEL4    (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
 136 #define P_SPI0_SSEL5    (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
 137 #define P_NAND_CE       (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
 138 #define P_NAND_WE       (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
 139 #define P_NAND_RE       (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
 140 #define P_NAND_RB       (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
 141 #define P_NAND_CLE      (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
 142 #define P_NAND_ALE      (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
 143
 144 #define P_HOST_D0       (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
 145 #define P_HOST_D1       (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
 146 #define P_HOST_D2       (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
 147 #define P_HOST_D3       (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
 148 #define P_HOST_D4       (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
 149 #define P_HOST_D5       (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(2))
 150 #define P_HOST_D6       (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
 151 #define P_HOST_D7       (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
 152 #define P_HOST_D8       (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
 153 #define P_HOST_D9       (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(2))
 154 #define P_HOST_D10      (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(2))
 155 #define P_HOST_D11      (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(2))
 156 #define P_HOST_D12      (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(2))
 157 #define P_HOST_D13      (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(2))
 158 #define P_HOST_D14      (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(2))
 159 #define P_HOST_D15      (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(2))
 160
 161 #define P_MII0_ETxD0    (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
 162 #define P_MII0_ETxD1    (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
 163 #define P_MII0_ETxD2    (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(1))
 164 #define P_MII0_ETxD3    (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(1))
 165 #define P_MII0_ETxEN    (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
 166 #define P_MII0_TxCLK    (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
 167 #define P_MII0_COL      (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
 168 #define P_MII0_ERxD0    (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
 169 #define P_MII0_ERxD1    (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(1))
 170 #define P_MII0_ERxD2    (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(1))
 171 #define P_MII0_ERxD3    (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(1))
 172 #define P_MII0_ERxDV    (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(1))
 173 #define P_MII0_ERxCLK   (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(1))
 174 #define P_MII0_ERxER    (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
 175 #define P_MII0_CRS      (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
 176 #define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
 177 #define P_RMII0_CRS_DV  (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
 178 #define P_MDIO          (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
 179
 180 #define P_TWI0_SCL      (P_DONTCARE)
 181 #define P_TWI0_SDA      (P_DONTCARE)
 182 #define P_PPI0_FS1      (P_DONTCARE)
 183 #define P_TMR0          (P_DONTCARE)
 184 #define P_TMRCLK        (P_DONTCARE)
 185 #define P_PPI0_CLK      (P_DONTCARE)
 186
 187 #define P_MII0 {\
 188         P_MII0_ETxD0, \
 189         P_MII0_ETxD1, \
 190         P_MII0_ETxD2, \
 191         P_MII0_ETxD3, \
 192         P_MII0_ETxEN, \
 193         P_MII0_TxCLK, \
 194         P_MII0_PHYINT, \
 195         P_MII0_COL, \
 196         P_MII0_ERxD0, \
 197         P_MII0_ERxD1, \
 198         P_MII0_ERxD2, \
 199         P_MII0_ERxD3, \
 200         P_MII0_ERxDV, \
 201         P_MII0_ERxCLK, \
 202         P_MII0_ERxER, \
 203         P_MII0_CRS, \
 204         P_MDC, \
 205         P_MDIO, 0}
 206
 207 #define P_RMII0 {\
 208         P_MII0_ETxD0, \
 209         P_MII0_ETxD1, \
 210         P_MII0_ETxEN, \
 211         P_MII0_ERxD0, \
 212         P_MII0_ERxD1, \
 213         P_MII0_ERxER, \
 214         P_RMII0_REF_CLK, \
 215         P_RMII0_MDINT, \
 216         P_RMII0_CRS_DV, \
 217         P_MDC, \
 218         P_MDIO, 0}
 219
 220 #endif                          /* _MACH_PORTMUX_H_ */