arch/blackfin/include/asm/mach-bf537/portmux.h

   1 /*
   2  * Copyright 2007-2009 Analog Devices Inc.
   3  *
   4  * Licensed under the GPL-2 or later
   5  */
   6
   7 #ifndef _MACH_PORTMUX_H_
   8 #define _MACH_PORTMUX_H_
   9
  10 #define MAX_RESOURCES   (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE)    /* We additionally handle PORTJ */
  11
  12 #define P_UART0_TX      (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
  13 #define P_UART0_RX      (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
  14 #define P_UART1_TX      (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
  15 #define P_UART1_RX      (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
  16 #define P_TMR5          (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
  17 #define P_TMR4          (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
  18 #define P_TMR3          (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
  19 #define P_TMR2          (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
  20 #define P_TMR1          (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
  21 #define P_TMR0          (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
  22 #define P_SPI0_SSEL1    (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
  23 #define P_SPI0_MOSI     (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
  24 #define P_SPI0_MISO     (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
  25 #define P_SPI0_SCK      (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
  26 #define P_SPI0_SS       (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
  27 #define P_PPI0_CLK      (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
  28 #define P_DMAR0         (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
  29 #define P_DMAR1         (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
  30 #define P_TMR7          (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
  31 #define P_TMR6          (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
  32 #define P_SPI0_SSEL6    (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
  33 #define P_SPI0_SSEL5    (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
  34 #define P_SPI0_SSEL4    (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
  35 #define P_PPI0_FS3      (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
  36 #define P_PPI0_FS2      (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
  37 #define P_PPI0_FS1      (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
  38 #define P_TACLK0        (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
  39 #define P_TMRCLK        (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
  40 #define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF10
  41 #define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
  42
  43 #define P_PPI0_D0       (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
  44 #define P_PPI0_D1       (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
  45 #define P_PPI0_D2       (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
  46 #define P_PPI0_D3       (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
  47 #define P_PPI0_D4       (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
  48 #define P_PPI0_D5       (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
  49 #define P_PPI0_D6       (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
  50 #define P_PPI0_D7       (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
  51 #define P_PPI0_D8       (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
  52 #define P_PPI0_D9       (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
  53 #define P_PPI0_D10      (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
  54 #define P_PPI0_D11      (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
  55 #define P_PPI0_D12      (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
  56 #define P_PPI0_D13      (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
  57 #define P_PPI0_D14      (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
  58 #define P_PPI0_D15      (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
  59 #define P_SPORT1_DRSEC  (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
  60 #define P_SPORT1_DTSEC  (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
  61 #define P_SPORT1_RSCLK  (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
  62 #define P_SPORT1_RFS    (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
  63 #define P_SPORT1_DRPRI  (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
  64 #define P_SPORT1_TSCLK  (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
  65 #define P_SPORT1_TFS    (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
  66 #define P_SPORT1_DTPRI  (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
  67
  68 #define P_MII0_ETxD0    (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
  69 #define P_MII0_ETxD1    (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
  70 #define P_MII0_ETxD2    (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
  71 #define P_MII0_ETxD3    (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
  72 #define P_MII0_ETxEN    (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
  73 #define P_MII0_TxCLK    (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
  74 #define P_MII0_PHYINT   (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
  75 #define P_MII0_COL      (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
  76 #define P_MII0_ERxD0    (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
  77 #define P_MII0_ERxD1    (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
  78 #define P_MII0_ERxD2    (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
  79 #define P_MII0_ERxD3    (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
  80 #define P_MII0_ERxDV    (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
  81 #define P_MII0_ERxCLK   (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
  82 #define P_MII0_ERxER    (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
  83 #define P_MII0_CRS      (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
  84 #define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
  85 #define P_RMII0_MDINT   (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
  86 #define P_RMII0_CRS_DV  (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
  87
  88 #define PORT_PJ0        (GPIO_PH15 + 1)
  89 #define PORT_PJ1        (GPIO_PH15 + 2)
  90 #define PORT_PJ2        (GPIO_PH15 + 3)
  91 #define PORT_PJ3        (GPIO_PH15 + 4)
  92 #define PORT_PJ4        (GPIO_PH15 + 5)
  93 #define PORT_PJ5        (GPIO_PH15 + 6)
  94 #define PORT_PJ6        (GPIO_PH15 + 7)
  95 #define PORT_PJ7        (GPIO_PH15 + 8)
  96 #define PORT_PJ8        (GPIO_PH15 + 9)
  97 #define PORT_PJ9        (GPIO_PH15 + 10)
  98 #define PORT_PJ10       (GPIO_PH15 + 11)
  99 #define PORT_PJ11       (GPIO_PH15 + 12)
 100
 101 #define P_MDC           (P_DEFINED | P_IDENT(PORT_PJ0) | P_FUNCT(0))
 102 #define P_MDIO          (P_DEFINED | P_IDENT(PORT_PJ1) | P_FUNCT(0))
 103 #define P_TWI0_SCL      (P_DEFINED | P_IDENT(PORT_PJ2) | P_FUNCT(0))
 104 #define P_TWI0_SDA      (P_DEFINED | P_IDENT(PORT_PJ3) | P_FUNCT(0))
 105 #define P_SPORT0_DRSEC  (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(0))
 106 #define P_SPORT0_DTSEC  (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(0))
 107 #define P_SPORT0_RSCLK  (P_DEFINED | P_IDENT(PORT_PJ6) | P_FUNCT(0))
 108 #define P_SPORT0_RFS    (P_DEFINED | P_IDENT(PORT_PJ7) | P_FUNCT(0))
 109 #define P_SPORT0_DRPRI  (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0))
 110 #define P_SPORT0_TSCLK  (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0))
 111 #define P_SPORT0_TFS    (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0))
 112 #define P_SPORT0_DTPRI  (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(0))
 113 #define P_CAN0_RX       (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1))
 114 #define P_CAN0_TX       (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1))
 115 #define P_SPI0_SSEL3    (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1))
 116 #define P_SPI0_SSEL2    (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1))
 117 #define P_SPI0_SSEL7    (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(2))
 118
 119 #define P_MII0 {\
 120         P_MII0_ETxD0, \
 121         P_MII0_ETxD1, \
 122         P_MII0_ETxD2, \
 123         P_MII0_ETxD3, \
 124         P_MII0_ETxEN, \
 125         P_MII0_TxCLK, \
 126         P_MII0_PHYINT, \
 127         P_MII0_COL, \
 128         P_MII0_ERxD0, \
 129         P_MII0_ERxD1, \
 130         P_MII0_ERxD2, \
 131         P_MII0_ERxD3, \
 132         P_MII0_ERxDV, \
 133         P_MII0_ERxCLK, \
 134         P_MII0_ERxER, \
 135         P_MII0_CRS, \
 136         P_MDC, \
 137         P_MDIO, 0}
 138
 139 #define P_RMII0 {\
 140         P_MII0_ETxD0, \
 141         P_MII0_ETxD1, \
 142         P_MII0_ETxEN, \
 143         P_MII0_ERxD0, \
 144         P_MII0_ERxD1, \
 145         P_MII0_ERxER, \
 146         P_RMII0_REF_CLK, \
 147         P_RMII0_MDINT, \
 148         P_RMII0_CRS_DV, \
 149         P_MDC, \
 150         P_MDIO, 0}
 151
 152 #endif /* _MACH_PORTMUX_H_ */