arch/blackfin/include/asm/mach-common/bits/dde.h

   1 /*
   2  * Distributed DMA Engine (DDE) Masks
   3  */
   4
   5 #ifndef __BFIN_PERIPHERAL_DDE__
   6 #define __BFIN_PERIPHERAL_DDE__
   7
   8 /* DMA_CONFIG Masks */
   9 #define DMAEN                   (1 << DMAEN_P)  /* DMA Channel Enable */
  10 #define WNR                     (1 << WNR_P)    /* Channel Direction (W/R*) */
  11 #define SYNC                    (1 << SYNC_P)   /* Sync Work Unit Transitions */
  12 #define CADDR                   (1 << CADDR_P)  /* Use Current Address */
  13 #define PSIZE                   (7 << PSIZE_P)  /* Peripheral Word Size */
  14 #define PSIZE_1                 (0 << PSIZE_P)
  15 #define PSIZE_2                 (1 << PSIZE_P)
  16 #define PSIZE_4                 (2 << PSIZE_P)
  17 #define PSIZE_8                 (3 << PSIZE_P)
  18 #define MSIZE                   (7 << MSIZE_P)  /* Memory Transfer Size */
  19 #define MSIZE_1                 (0 << MSIZE_P)
  20 #define MSIZE_2                 (1 << MSIZE_P)
  21 #define MSIZE_4                 (2 << MSIZE_P)
  22 #define MSIZE_8                 (3 << MSIZE_P)
  23 #define MSIZE_16                (4 << MSIZE_P)
  24 #define MSIZE_32                (5 << MSIZE_P)
  25 #define FLOW                    (7 << FLOW_P)   /* Next Operation */
  26 #define FLOW_STOP               (0 << FLOW_P)   /* Stop Mode */
  27 #define FLOW_AUTO               (1 << FLOW_P)   /* Autobuffer Mode */
  28 #define FLOW_DSCL               (4 << FLOW_P)   /* Descriptor List */
  29 #define FLOW_DSCA               (5 << FLOW_P)   /* Descriptor Array */
  30 #define FLOW_DSDL               (6 << FLOW_P)   /* Descriptor On Demand List */
  31 #define FLOW_DSDA               (7 << FLOW_P)   /* Descriptor On Demand Array */
  32 #define NDSIZE                  (7 << NDSIZE_P) /* Next Descriptor Set Size */
  33 #define NDSIZE_1                (0 << NDSIZE_P)
  34 #define NDSIZE_2                (1 << NDSIZE_P)
  35 #define NDSIZE_3                (2 << NDSIZE_P)
  36 #define NDSIZE_4                (3 << NDSIZE_P)
  37 #define NDSIZE_5                (4 << NDSIZE_P)
  38 #define NDSIZE_6                (5 << NDSIZE_P)
  39 #define NDSIZE_7                (6 << NDSIZE_P)
  40 #define DI_EN_X                 (1 << INT_P)
  41 #define DI_EN_Y                 (2 << INT_P)
  42 #define DI_EN_P                 (3 << INT_P)
  43 #define DI_EN                   (DI_EN_X)
  44 #define DI_XCOUNT_EN            (1 << INT_P)    /* xcount expires interrupt */
  45 #define TRIG                    (3 << TRIG_P)   /* Generate Trigger */
  46 #define TOVEN                   (1 << TOVEN_P)
  47 #define DESCIDCPY               (1 << DESCIDCPY_P)
  48 #define TWOD                    (1 << TWOD_P)
  49 #define PDRF                    (1 << PDRF_P)
  50
  51 #define DMAEN_P                 0
  52 #define WNR_P                   1
  53 #define SYNC_P                  2
  54 #define CADDR_P                 3
  55 #define PSIZE_P                 4
  56 #define MSIZE_P                 8
  57 #define FLOW_P                  12
  58 #define TWAIT_P                 15
  59 #define NDSIZE_P                16
  60 #define INT_P                   20
  61 #define TRIG_P                  22
  62 #define TOVEN_P                 24
  63 #define DESCIDCPY_P             25
  64 #define TWOD_P                  26
  65 #define PDRF_P                  28
  66
  67 /* DMA_STATUS Masks */
  68 #define DMA_DONE                (1 << DMA_DONE_P)       /* Work Unit/Row Done */
  69 #define DMA_ERR                 (1 << DMA_ERR_P)        /* Error Interrupt */
  70 #define DMA_PIRQ                (1 << DMA_PIRQ_P)       /* Peri Intr Request */
  71 #define DMA_ERRC                (7 << DMA_ERRC_P)       /* Error Cause */
  72 #define DMA_RUN                 (7 << DMA_RUN_P)        /* Run Status */
  73 #define DMA_PBWIDTH             (3 << DMA_PBWIDTH_P)    /* Peri Bus Width */
  74 #define DMA_MBWIDTH             (3 << DMA_MBWIDTH_P)    /* Memory Bus Width */
  75 #define DMA_FIFOFILL            (7 << DMA_FIFOFILL_P)   /* FIFO Fill Status */
  76 #define DMA_TWAIT               (1 << DMA_TWAIT_P)      /* Trigger Wait Stat */
  77
  78 #define DMA_DONE_P              0
  79 #define DMA_ERR_P               1
  80 #define DMA_PIRQ_P              2
  81 #define DMA_ERRC_P              4
  82 #define DMA_RUN_P               8
  83 #define DMA_PBWIDTH_P           12
  84 #define DMA_MBWIDTH_P           14
  85 #define DMA_FIFOFILL_P          16
  86 #define DMA_TWAIT_P             20
  87
  88 #endif