arch/blackfin/include/asm/mach-common/bits/sdh.h

   1 /*
   2  * SDH Masks
   3  */
   4
   5 #ifndef __BFIN_PERIPHERAL_SDH__
   6 #define __BFIN_PERIPHERAL_SDH__
   7
   8 /* Bit masks for SDH_COMMAND */
   9 #define                   CMD_IDX  0x3f       /* Command Index */
  10 #define                   CMD_RSP  0x40       /* Response */
  11 #define                 CMD_L_RSP  0x80       /* Long Response */
  12 #define                 CMD_INT_E  0x100      /* Command Interrupt */
  13 #define                CMD_PEND_E  0x200      /* Command Pending */
  14 #define                     CMD_E  0x400      /* Command Enable */
  15
  16 /* Bit masks for SDH_PWR_CTL */
  17 #define                    PWR_ON  0x3        /* Power On */
  18 #define                 SD_CMD_OD  0x40       /* Open Drain Output */
  19 #define                   ROD_CTL  0x80       /* Rod Control */
  20
  21 /* Bit masks for SDH_CLK_CTL */
  22 #define                    CLKDIV  0xff       /* MC_CLK Divisor */
  23 #define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
  24 #define                  PWR_SV_E  0x200      /* Power Save Enable */
  25 #define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
  26 #define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
  27
  28 /* Bit masks for SDH_RESP_CMD */
  29 #define                  RESP_CMD  0x3f       /* Response Command */
  30
  31 /* Bit masks for SDH_DATA_CTL */
  32 #define                     DTX_E  0x1        /* Data Transfer Enable */
  33 #define                   DTX_DIR  0x2        /* Data Transfer Direction */
  34 #define                  DTX_MODE  0x4        /* Data Transfer Mode */
  35 #define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
  36 #define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
  37
  38 /* Bit masks for SDH_STATUS */
  39 #define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
  40 #define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
  41 #define              CMD_TIME_OUT  0x4        /* CMD Time Out */
  42 #define              DAT_TIME_OUT  0x8        /* Data Time Out */
  43 #define               TX_UNDERRUN  0x10       /* Transmit Underrun */
  44 #define                RX_OVERRUN  0x20       /* Receive Overrun */
  45 #define              CMD_RESP_END  0x40       /* CMD Response End */
  46 #define                  CMD_SENT  0x80       /* CMD Sent */
  47 #define                   DAT_END  0x100      /* Data End */
  48 #define             START_BIT_ERR  0x200      /* Start Bit Error */
  49 #define               DAT_BLK_END  0x400      /* Data Block End */
  50 #define                   CMD_ACT  0x800      /* CMD Active */
  51 #define                    TX_ACT  0x1000     /* Transmit Active */
  52 #define                    RX_ACT  0x2000     /* Receive Active */
  53 #define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
  54 #define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
  55 #define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
  56 #define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
  57 #define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
  58 #define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
  59 #define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
  60 #define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
  61
  62 /* Bit masks for SDH_STATUS_CLR */
  63 #define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
  64 #define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
  65 #define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
  66 #define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
  67 #define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
  68 #define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
  69 #define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
  70 #define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
  71 #define              DAT_END_STAT  0x100      /* Data End Status */
  72 #define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
  73 #define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
  74
  75 /* Bit masks for SDH_MASK0 */
  76 #define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
  77 #define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
  78 #define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
  79 #define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
  80 #define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
  81 #define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
  82 #define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
  83 #define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
  84 #define              DAT_END_MASK  0x100      /* Data End Mask */
  85 #define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
  86 #define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
  87 #define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
  88 #define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
  89 #define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
  90 #define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
  91 #define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
  92 #define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
  93 #define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
  94 #define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
  95 #define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
  96 #define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
  97 #define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
  98
  99 /* Bit masks for SDH_FIFO_CNT */
 100 #define                FIFO_COUNT  0x7fff     /* FIFO Count */
 101
 102 /* Bit masks for SDH_E_STATUS */
 103 #define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
 104 #define               SD_CARD_DET  0x10       /* SD Card Detect */
 105
 106 /* Bit masks for SDH_E_MASK */
 107 #define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
 108 #define                   SCD_MSK  0x40       /* Mask Card Detect */
 109
 110 /* Bit masks for SDH_CFG */
 111 #define                   CLKS_EN  0x1        /* Clocks Enable */
 112 #define                      SD4E  0x4        /* SDIO 4-Bit Enable */
 113 #define                       MWE  0x8        /* Moving Window Enable */
 114 #define                    SD_RST  0x10       /* SDMMC Reset */
 115 #define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
 116 #define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
 117 #define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
 118
 119 /* Bit masks for SDH_RD_WAIT_EN */
 120 #define                       RWR  0x1        /* Read Wait Request */
 121
 122 #endif