arch/blackfin/lib/u-boot.lds.S

   1 /*
   2  * U-boot - u-boot.lds.S
   3  *
   4  * Copyright (c) 2005-2010 Analog Device Inc.
   5  *
   6  * (C) Copyright 2000-2004
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <config.h>
  29 #include <asm/blackfin.h>
  30 #undef ALIGN
  31 #undef ENTRY
  32
  33 #ifndef LDS_BOARD_TEXT
  34 # define LDS_BOARD_TEXT
  35 #endif
  36
  37 /* If we don't actually load anything into L1 data, this will avoid
  38  * a syntax error.  If we do actually load something into L1 data,
  39  * we'll get a linker memory load error (which is what we'd want).
  40  * This is here in the first place so we can quickly test building
  41  * for different CPU's which may lack non-cache L1 data.
  42  */
  43 #ifndef L1_DATA_A_SRAM
  44 # define L1_DATA_A_SRAM      0
  45 # define L1_DATA_A_SRAM_SIZE 0
  46 #endif
  47 #ifndef L1_DATA_B_SRAM
  48 # define L1_DATA_B_SRAM      L1_DATA_A_SRAM
  49 # define L1_DATA_B_SRAM_SIZE L1_DATA_A_SRAM_SIZE
  50 #endif
  51
  52 /* The 0xC offset is so we don't clobber the tiny LDR jump block. */
  53 #ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
  54 # define L1_CODE_ORIGIN L1_INST_SRAM
  55 #else
  56 # define L1_CODE_ORIGIN L1_INST_SRAM + 0xC
  57 #endif
  58
  59 OUTPUT_ARCH(bfin)
  60
  61 MEMORY
  62 {
  63 #if CONFIG_MEM_SIZE
  64         ram     : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
  65 # define ram_code ram
  66 # define ram_data ram
  67 #else
  68 # define ram_code l1_code
  69 # define ram_data l1_data
  70 #endif
  71         l1_code : ORIGIN = L1_CODE_ORIGIN,          LENGTH = L1_INST_SRAM_SIZE
  72         l1_data : ORIGIN = L1_DATA_B_SRAM,          LENGTH = L1_DATA_B_SRAM_SIZE
  73 }
  74
  75 ENTRY(_start)
  76 SECTIONS
  77 {
  78         .text.pre :
  79         {
  80                 arch/blackfin/cpu/start.o (.text .text.*)
  81
  82                 LDS_BOARD_TEXT
  83         } >ram_code
  84
  85         .text.init :
  86         {
  87                 arch/blackfin/cpu/initcode.o (.text .text.*)
  88         } >ram_code
  89         __initcode_lma = LOADADDR(.text.init);
  90         __initcode_len = SIZEOF(.text.init);
  91
  92         .text :
  93         {
  94                 *(.text .text.*)
  95         } >ram_code
  96
  97         .rodata :
  98         {
  99                 . = ALIGN(4);
 100                 *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
 101                 . = ALIGN(4);
 102         } >ram_data
 103
 104         .data :
 105         {
 106                 . = ALIGN(4);
 107                 *(.data .data.*)
 108                 *(.data1)
 109                 *(.sdata)
 110                 *(.sdata2)
 111                 *(.dynamic)
 112                 CONSTRUCTORS
 113         } >ram_data
 114
 115         .u_boot_cmd :
 116         {
 117                 ___u_boot_cmd_start = .;
 118                 *(.u_boot_cmd)
 119                 ___u_boot_cmd_end = .;
 120         } >ram_data
 121
 122         .text_l1 :
 123         {
 124                 . = ALIGN(4);
 125                 __stext_l1 = .;
 126                 *(.l1.text)
 127                 . = ALIGN(4);
 128                 __etext_l1 = .;
 129         } >l1_code AT>ram_code
 130         __text_l1_lma = LOADADDR(.text_l1);
 131         __text_l1_len = SIZEOF(.text_l1);
 132         ASSERT (__text_l1_len <= L1_INST_SRAM_SIZE, "L1 text overflow!")
 133
 134         .data_l1 :
 135         {
 136                 . = ALIGN(4);
 137                 __sdata_l1 = .;
 138                 *(.l1.data)
 139                 *(.l1.bss)
 140                 . = ALIGN(4);
 141                 __edata_l1 = .;
 142         } >l1_data AT>ram_data
 143         __data_l1_lma = LOADADDR(.data_l1);
 144         __data_l1_len = SIZEOF(.data_l1);
 145         ASSERT (__data_l1_len <= L1_DATA_B_SRAM_SIZE, "L1 data overflow!")
 146
 147         .bss :
 148         {
 149                 . = ALIGN(4);
 150                 *(.sbss) *(.scommon)
 151                 *(.dynbss)
 152                 *(.bss .bss.*)
 153                 *(COMMON)
 154                 . = ALIGN(4);
 155         } >ram_data
 156         __bss_vma = ADDR(.bss);
 157         __bss_len = SIZEOF(.bss);
 158 }