arch/i386/cpu/interrupts.c

   1 /*
   2  * (C) Copyright 2008-2011
   3  * Graeme Russ, <graeme.russ@gmail.com>
   4  *
   5  * (C) Copyright 2002
   6  * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
   7  *
   8  * Portions of this file are derived from the Linux kernel source
   9  *  Copyright (C) 1991, 1992  Linus Torvalds
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #include <common.h>
  31 #include <asm/interrupt.h>
  32 #include <asm/io.h>
  33 #include <asm/processor-flags.h>
  34
  35 #define DECLARE_INTERRUPT(x) \
  36         ".globl irq_"#x"\n" \
  37         ".hidden irq_"#x"\n" \
  38         ".type irq_"#x", @function\n" \
  39         "irq_"#x":\n" \
  40         "pushl $"#x"\n" \
  41         "jmp irq_common_entry\n"
  42
  43 /*
  44  * Volatile isn't enough to prevent the compiler from reordering the
  45  * read/write functions for the control registers and messing everything up.
  46  * A memory clobber would solve the problem, but would prevent reordering of
  47  * all loads stores around it, which can hurt performance. Solution is to
  48  * use a variable and mimic reads and writes to it to enforce serialisation
  49  */
  50 static unsigned long __force_order;
  51
  52 static inline unsigned long read_cr0(void)
  53 {
  54         unsigned long val;
  55         asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order));
  56         return val;
  57 }
  58
  59 static inline unsigned long read_cr2(void)
  60 {
  61         unsigned long val;
  62         asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order));
  63         return val;
  64 }
  65
  66 static inline unsigned long read_cr3(void)
  67 {
  68         unsigned long val;
  69         asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order));
  70         return val;
  71 }
  72
  73 static inline unsigned long read_cr4(void)
  74 {
  75         unsigned long val;
  76         asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order));
  77         return val;
  78 }
  79
  80 static inline unsigned long get_debugreg(int regno)
  81 {
  82         unsigned long val = 0;  /* Damn you, gcc! */
  83
  84         switch (regno) {
  85         case 0:
  86                 asm("mov %%db0, %0" :"=r" (val));
  87                 break;
  88         case 1:
  89                 asm("mov %%db1, %0" :"=r" (val));
  90                 break;
  91         case 2:
  92                 asm("mov %%db2, %0" :"=r" (val));
  93                 break;
  94         case 3:
  95                 asm("mov %%db3, %0" :"=r" (val));
  96                 break;
  97         case 6:
  98                 asm("mov %%db6, %0" :"=r" (val));
  99                 break;
 100         case 7:
 101                 asm("mov %%db7, %0" :"=r" (val));
 102                 break;
 103         default:
 104                 val = 0;
 105         }
 106         return val;
 107 }
 108
 109 void dump_regs(struct irq_regs *regs)
 110 {
 111         unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
 112         unsigned long d0, d1, d2, d3, d6, d7;
 113         unsigned long sp;
 114
 115         printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n",
 116                         (u16)regs->xcs, regs->eip, regs->eflags);
 117
 118         printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
 119                 regs->eax, regs->ebx, regs->ecx, regs->edx);
 120         printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
 121                 regs->esi, regs->edi, regs->ebp, regs->esp);
 122         printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
 123                (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs, (u16)regs->xgs, (u16)regs->xss);
 124
 125         cr0 = read_cr0();
 126         cr2 = read_cr2();
 127         cr3 = read_cr3();
 128         cr4 = read_cr4();
 129
 130         printf("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
 131                         cr0, cr2, cr3, cr4);
 132
 133         d0 = get_debugreg(0);
 134         d1 = get_debugreg(1);
 135         d2 = get_debugreg(2);
 136         d3 = get_debugreg(3);
 137
 138         printf("DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
 139                         d0, d1, d2, d3);
 140
 141         d6 = get_debugreg(6);
 142         d7 = get_debugreg(7);
 143         printf("DR6: %08lx DR7: %08lx\n",
 144                         d6, d7);
 145
 146         printf("Stack:\n");
 147         sp = regs->esp;
 148
 149         sp += 64;
 150
 151         while (sp > (regs->esp - 16)) {
 152                 if (sp == regs->esp)
 153                         printf("--->");
 154                 else
 155                         printf("    ");
 156                 printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp));
 157                 sp -= 4;
 158         }
 159 }
 160
 161 struct idt_entry {
 162         u16     base_low;
 163         u16     selector;
 164         u8      res;
 165         u8      access;
 166         u16     base_high;
 167 } __attribute__ ((packed));
 168
 169 struct desc_ptr {
 170         unsigned short size;
 171         unsigned long address;
 172         unsigned short segment;
 173 } __attribute__((packed));
 174
 175 struct idt_entry idt[256];
 176
 177 struct desc_ptr idt_ptr;
 178
 179 static inline void load_idt(const struct desc_ptr *dtr)
 180 {
 181         asm volatile("cs lidt %0"::"m" (*dtr));
 182 }
 183
 184 void set_vector(u8 intnum, void *routine)
 185 {
 186         idt[intnum].base_high = (u16)((u32)(routine) >> 16);
 187         idt[intnum].base_low = (u16)((u32)(routine) & 0xffff);
 188 }
 189
 190 void irq_0(void);
 191 void irq_1(void);
 192
 193 int cpu_init_interrupts(void)
 194 {
 195         int i;
 196
 197         int irq_entry_size = irq_1 - irq_0;
 198         void *irq_entry = (void *)irq_0;
 199
 200         /* Just in case... */
 201         disable_interrupts();
 202
 203         /* Setup the IDT */
 204         for (i=0;i<256;i++) {
 205                 idt[i].access = 0x8e;
 206                 idt[i].res = 0;
 207                 idt[i].selector = 0x10;
 208                 set_vector(i, irq_entry);
 209                 irq_entry += irq_entry_size;
 210         }
 211
 212         idt_ptr.size = 256 * 8;
 213         idt_ptr.address = (unsigned long) idt;
 214         idt_ptr.segment = 0x18;
 215
 216         load_idt(&idt_ptr);
 217
 218         /* It is now safe to enable interrupts */
 219         enable_interrupts();
 220
 221         return 0;
 222 }
 223
 224 void __do_irq(int irq)
 225 {
 226         printf("Unhandled IRQ : %d\n", irq);
 227 }
 228 void do_irq(int irq) __attribute__((weak, alias("__do_irq")));
 229
 230 void enable_interrupts(void)
 231 {
 232         asm("sti\n");
 233 }
 234
 235 int disable_interrupts(void)
 236 {
 237         long flags;
 238
 239         asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
 240
 241         return flags & X86_EFLAGS_IF; /* IE flags is bit 9 */
 242 }
 243
 244 /* IRQ Low-Level Service Routine */
 245 void irq_llsr(struct irq_regs *regs)
 246 {
 247         /*
 248          * For detailed description of each exception, refer to:
 249          * Intel® 64 and IA-32 Architectures Software Developer's Manual
 250          * Volume 1: Basic Architecture
 251          * Order Number: 253665-029US, November 2008
 252          * Table 6-1. Exceptions and Interrupts
 253          */
 254         switch (regs->irq_id) {
 255         case 0x00:
 256                 printf("Divide Error (Division by zero)\n");
 257                 dump_regs(regs);
 258                 while(1);
 259                 break;
 260         case 0x01:
 261                 printf("Debug Interrupt (Single step)\n");
 262                 dump_regs(regs);
 263                 break;
 264         case 0x02:
 265                 printf("NMI Interrupt\n");
 266                 dump_regs(regs);
 267                 break;
 268         case 0x03:
 269                 printf("Breakpoint\n");
 270                 dump_regs(regs);
 271                 break;
 272         case 0x04:
 273                 printf("Overflow\n");
 274                 dump_regs(regs);
 275                 while(1);
 276                 break;
 277         case 0x05:
 278                 printf("BOUND Range Exceeded\n");
 279                 dump_regs(regs);
 280                 while(1);
 281                 break;
 282         case 0x06:
 283                 printf("Invalid Opcode (UnDefined Opcode)\n");
 284                 dump_regs(regs);
 285                 while(1);
 286                 break;
 287         case 0x07:
 288                 printf("Device Not Available (No Math Coprocessor)\n");
 289                 dump_regs(regs);
 290                 while(1);
 291                 break;
 292         case 0x08:
 293                 printf("Double fault\n");
 294                 dump_regs(regs);
 295                 while(1);
 296                 break;
 297         case 0x09:
 298                 printf("Co-processor segment overrun\n");
 299                 dump_regs(regs);
 300                 while(1);
 301                 break;
 302         case 0x0a:
 303                 printf("Invalid TSS\n");
 304                 dump_regs(regs);
 305                 break;
 306         case 0x0b:
 307                 printf("Segment Not Present\n");
 308                 dump_regs(regs);
 309                 while(1);
 310                 break;
 311         case 0x0c:
 312                 printf("Stack Segment Fault\n");
 313                 dump_regs(regs);
 314                 while(1);
 315                 break;
 316         case 0x0d:
 317                 printf("General Protection\n");
 318                 dump_regs(regs);
 319                 break;
 320         case 0x0e:
 321                 printf("Page fault\n");
 322                 dump_regs(regs);
 323                 while(1);
 324                 break;
 325         case 0x0f:
 326                 printf("Floating-Point Error (Math Fault)\n");
 327                 dump_regs(regs);
 328                 break;
 329         case 0x10:
 330                 printf("Alignment check\n");
 331                 dump_regs(regs);
 332                 break;
 333         case 0x11:
 334                 printf("Machine Check\n");
 335                 dump_regs(regs);
 336                 break;
 337         case 0x12:
 338                 printf("SIMD Floating-Point Exception\n");
 339                 dump_regs(regs);
 340                 break;
 341         case 0x13:
 342         case 0x14:
 343         case 0x15:
 344         case 0x16:
 345         case 0x17:
 346         case 0x18:
 347         case 0x19:
 348         case 0x1a:
 349         case 0x1b:
 350         case 0x1c:
 351         case 0x1d:
 352         case 0x1e:
 353         case 0x1f:
 354                 printf("Reserved Exception\n");
 355                 dump_regs(regs);
 356                 break;
 357
 358         default:
 359                 /* Hardware or User IRQ */
 360                 do_irq(regs->irq_id);
 361         }
 362 }
 363
 364 /*
 365  * OK - This looks really horrible, but it serves a purpose - It helps create
 366  * fully relocatable code.
 367  *  - The call to irq_llsr will be a relative jump
 368  *  - The IRQ entries will be guaranteed to be in order
 369  *  Interrupt entries are now very small (a push and a jump) but they are
 370  *  now slower (all registers pushed on stack which provides complete
 371  *  crash dumps in the low level handlers
 372  *
 373  * Interrupt Entry Point:
 374  *  - Interrupt has caused eflags, CS and EIP to be pushed
 375  *  - Interrupt Vector Handler has pushed orig_eax
 376  *  - pt_regs.esp needs to be adjusted by 40 bytes:
 377  *      12 bytes pushed by CPU (EFLAGSF, CS, EIP)
 378  *      4 bytes pushed by vector handler (irq_id)
 379  *      24 bytes pushed before SP (SS, GS, FS, ES, DS, EAX)
 380  *      NOTE: Only longs are pushed on/popped off the stack!
 381  */
 382 asm(".globl irq_common_entry\n" \
 383         ".hidden irq_common_entry\n" \
 384         ".type irq_common_entry, @function\n" \
 385         "irq_common_entry:\n" \
 386         "cld\n" \
 387         "pushl %ss\n" \
 388         "pushl %gs\n" \
 389         "pushl %fs\n" \
 390         "pushl %es\n" \
 391         "pushl %ds\n" \
 392         "pushl %eax\n" \
 393         "movl  %esp, %eax\n" \
 394         "addl  $40, %eax\n" \
 395         "pushl %eax\n" \
 396         "pushl %ebp\n" \
 397         "pushl %edi\n" \
 398         "pushl %esi\n" \
 399         "pushl %edx\n" \
 400         "pushl %ecx\n" \
 401         "pushl %ebx\n" \
 402         "mov   %esp, %eax\n" \
 403         "call irq_llsr\n" \
 404         "popl %ebx\n" \
 405         "popl %ecx\n" \
 406         "popl %edx\n" \
 407         "popl %esi\n" \
 408         "popl %edi\n" \
 409         "popl %ebp\n" \
 410         "popl %eax\n" \
 411         "popl %eax\n" \
 412         "popl %ds\n" \
 413         "popl %es\n" \
 414         "popl %fs\n" \
 415         "popl %gs\n" \
 416         "popl %ss\n" \
 417         "add  $4, %esp\n" \
 418         "iret\n" \
 419         DECLARE_INTERRUPT(0) \
 420         DECLARE_INTERRUPT(1) \
 421         DECLARE_INTERRUPT(2) \
 422         DECLARE_INTERRUPT(3) \
 423         DECLARE_INTERRUPT(4) \
 424         DECLARE_INTERRUPT(5) \
 425         DECLARE_INTERRUPT(6) \
 426         DECLARE_INTERRUPT(7) \
 427         DECLARE_INTERRUPT(8) \
 428         DECLARE_INTERRUPT(9) \
 429         DECLARE_INTERRUPT(10) \
 430         DECLARE_INTERRUPT(11) \
 431         DECLARE_INTERRUPT(12) \
 432         DECLARE_INTERRUPT(13) \
 433         DECLARE_INTERRUPT(14) \
 434         DECLARE_INTERRUPT(15) \
 435         DECLARE_INTERRUPT(16) \
 436         DECLARE_INTERRUPT(17) \
 437         DECLARE_INTERRUPT(18) \
 438         DECLARE_INTERRUPT(19) \
 439         DECLARE_INTERRUPT(20) \
 440         DECLARE_INTERRUPT(21) \
 441         DECLARE_INTERRUPT(22) \
 442         DECLARE_INTERRUPT(23) \
 443         DECLARE_INTERRUPT(24) \
 444         DECLARE_INTERRUPT(25) \
 445         DECLARE_INTERRUPT(26) \
 446         DECLARE_INTERRUPT(27) \
 447         DECLARE_INTERRUPT(28) \
 448         DECLARE_INTERRUPT(29) \
 449         DECLARE_INTERRUPT(30) \
 450         DECLARE_INTERRUPT(31) \
 451         DECLARE_INTERRUPT(32) \
 452         DECLARE_INTERRUPT(33) \
 453         DECLARE_INTERRUPT(34) \
 454         DECLARE_INTERRUPT(35) \
 455         DECLARE_INTERRUPT(36) \
 456         DECLARE_INTERRUPT(37) \
 457         DECLARE_INTERRUPT(38) \
 458         DECLARE_INTERRUPT(39) \
 459         DECLARE_INTERRUPT(40) \
 460         DECLARE_INTERRUPT(41) \
 461         DECLARE_INTERRUPT(42) \
 462         DECLARE_INTERRUPT(43) \
 463         DECLARE_INTERRUPT(44) \
 464         DECLARE_INTERRUPT(45) \
 465         DECLARE_INTERRUPT(46) \
 466         DECLARE_INTERRUPT(47) \
 467         DECLARE_INTERRUPT(48) \
 468         DECLARE_INTERRUPT(49) \
 469         DECLARE_INTERRUPT(50) \
 470         DECLARE_INTERRUPT(51) \
 471         DECLARE_INTERRUPT(52) \
 472         DECLARE_INTERRUPT(53) \
 473         DECLARE_INTERRUPT(54) \
 474         DECLARE_INTERRUPT(55) \
 475         DECLARE_INTERRUPT(56) \
 476         DECLARE_INTERRUPT(57) \
 477         DECLARE_INTERRUPT(58) \
 478         DECLARE_INTERRUPT(59) \
 479         DECLARE_INTERRUPT(60) \
 480         DECLARE_INTERRUPT(61) \
 481         DECLARE_INTERRUPT(62) \
 482         DECLARE_INTERRUPT(63) \
 483         DECLARE_INTERRUPT(64) \
 484         DECLARE_INTERRUPT(65) \
 485         DECLARE_INTERRUPT(66) \
 486         DECLARE_INTERRUPT(67) \
 487         DECLARE_INTERRUPT(68) \
 488         DECLARE_INTERRUPT(69) \
 489         DECLARE_INTERRUPT(70) \
 490         DECLARE_INTERRUPT(71) \
 491         DECLARE_INTERRUPT(72) \
 492         DECLARE_INTERRUPT(73) \
 493         DECLARE_INTERRUPT(74) \
 494         DECLARE_INTERRUPT(75) \
 495         DECLARE_INTERRUPT(76) \
 496         DECLARE_INTERRUPT(77) \
 497         DECLARE_INTERRUPT(78) \
 498         DECLARE_INTERRUPT(79) \
 499         DECLARE_INTERRUPT(80) \
 500         DECLARE_INTERRUPT(81) \
 501         DECLARE_INTERRUPT(82) \
 502         DECLARE_INTERRUPT(83) \
 503         DECLARE_INTERRUPT(84) \
 504         DECLARE_INTERRUPT(85) \
 505         DECLARE_INTERRUPT(86) \
 506         DECLARE_INTERRUPT(87) \
 507         DECLARE_INTERRUPT(88) \
 508         DECLARE_INTERRUPT(89) \
 509         DECLARE_INTERRUPT(90) \
 510         DECLARE_INTERRUPT(91) \
 511         DECLARE_INTERRUPT(92) \
 512         DECLARE_INTERRUPT(93) \
 513         DECLARE_INTERRUPT(94) \
 514         DECLARE_INTERRUPT(95) \
 515         DECLARE_INTERRUPT(97) \
 516         DECLARE_INTERRUPT(96) \
 517         DECLARE_INTERRUPT(98) \
 518         DECLARE_INTERRUPT(99) \
 519         DECLARE_INTERRUPT(100) \
 520         DECLARE_INTERRUPT(101) \
 521         DECLARE_INTERRUPT(102) \
 522         DECLARE_INTERRUPT(103) \
 523         DECLARE_INTERRUPT(104) \
 524         DECLARE_INTERRUPT(105) \
 525         DECLARE_INTERRUPT(106) \
 526         DECLARE_INTERRUPT(107) \
 527         DECLARE_INTERRUPT(108) \
 528         DECLARE_INTERRUPT(109) \
 529         DECLARE_INTERRUPT(110) \
 530         DECLARE_INTERRUPT(111) \
 531         DECLARE_INTERRUPT(112) \
 532         DECLARE_INTERRUPT(113) \
 533         DECLARE_INTERRUPT(114) \
 534         DECLARE_INTERRUPT(115) \
 535         DECLARE_INTERRUPT(116) \
 536         DECLARE_INTERRUPT(117) \
 537         DECLARE_INTERRUPT(118) \
 538         DECLARE_INTERRUPT(119) \
 539         DECLARE_INTERRUPT(120) \
 540         DECLARE_INTERRUPT(121) \
 541         DECLARE_INTERRUPT(122) \
 542         DECLARE_INTERRUPT(123) \
 543         DECLARE_INTERRUPT(124) \
 544         DECLARE_INTERRUPT(125) \
 545         DECLARE_INTERRUPT(126) \
 546         DECLARE_INTERRUPT(127) \
 547         DECLARE_INTERRUPT(128) \
 548         DECLARE_INTERRUPT(129) \
 549         DECLARE_INTERRUPT(130) \
 550         DECLARE_INTERRUPT(131) \
 551         DECLARE_INTERRUPT(132) \
 552         DECLARE_INTERRUPT(133) \
 553         DECLARE_INTERRUPT(134) \
 554         DECLARE_INTERRUPT(135) \
 555         DECLARE_INTERRUPT(136) \
 556         DECLARE_INTERRUPT(137) \
 557         DECLARE_INTERRUPT(138) \
 558         DECLARE_INTERRUPT(139) \
 559         DECLARE_INTERRUPT(140) \
 560         DECLARE_INTERRUPT(141) \
 561         DECLARE_INTERRUPT(142) \
 562         DECLARE_INTERRUPT(143) \
 563         DECLARE_INTERRUPT(144) \
 564         DECLARE_INTERRUPT(145) \
 565         DECLARE_INTERRUPT(146) \
 566         DECLARE_INTERRUPT(147) \
 567         DECLARE_INTERRUPT(148) \
 568         DECLARE_INTERRUPT(149) \
 569         DECLARE_INTERRUPT(150) \
 570         DECLARE_INTERRUPT(151) \
 571         DECLARE_INTERRUPT(152) \
 572         DECLARE_INTERRUPT(153) \
 573         DECLARE_INTERRUPT(154) \
 574         DECLARE_INTERRUPT(155) \
 575         DECLARE_INTERRUPT(156) \
 576         DECLARE_INTERRUPT(157) \
 577         DECLARE_INTERRUPT(158) \
 578         DECLARE_INTERRUPT(159) \
 579         DECLARE_INTERRUPT(160) \
 580         DECLARE_INTERRUPT(161) \
 581         DECLARE_INTERRUPT(162) \
 582         DECLARE_INTERRUPT(163) \
 583         DECLARE_INTERRUPT(164) \
 584         DECLARE_INTERRUPT(165) \
 585         DECLARE_INTERRUPT(166) \
 586         DECLARE_INTERRUPT(167) \
 587         DECLARE_INTERRUPT(168) \
 588         DECLARE_INTERRUPT(169) \
 589         DECLARE_INTERRUPT(170) \
 590         DECLARE_INTERRUPT(171) \
 591         DECLARE_INTERRUPT(172) \
 592         DECLARE_INTERRUPT(173) \
 593         DECLARE_INTERRUPT(174) \
 594         DECLARE_INTERRUPT(175) \
 595         DECLARE_INTERRUPT(176) \
 596         DECLARE_INTERRUPT(177) \
 597         DECLARE_INTERRUPT(178) \
 598         DECLARE_INTERRUPT(179) \
 599         DECLARE_INTERRUPT(180) \
 600         DECLARE_INTERRUPT(181) \
 601         DECLARE_INTERRUPT(182) \
 602         DECLARE_INTERRUPT(183) \
 603         DECLARE_INTERRUPT(184) \
 604         DECLARE_INTERRUPT(185) \
 605         DECLARE_INTERRUPT(186) \
 606         DECLARE_INTERRUPT(187) \
 607         DECLARE_INTERRUPT(188) \
 608         DECLARE_INTERRUPT(189) \
 609         DECLARE_INTERRUPT(190) \
 610         DECLARE_INTERRUPT(191) \
 611         DECLARE_INTERRUPT(192) \
 612         DECLARE_INTERRUPT(193) \
 613         DECLARE_INTERRUPT(194) \
 614         DECLARE_INTERRUPT(195) \
 615         DECLARE_INTERRUPT(196) \
 616         DECLARE_INTERRUPT(197) \
 617         DECLARE_INTERRUPT(198) \
 618         DECLARE_INTERRUPT(199) \
 619         DECLARE_INTERRUPT(200) \
 620         DECLARE_INTERRUPT(201) \
 621         DECLARE_INTERRUPT(202) \
 622         DECLARE_INTERRUPT(203) \
 623         DECLARE_INTERRUPT(204) \
 624         DECLARE_INTERRUPT(205) \
 625         DECLARE_INTERRUPT(206) \
 626         DECLARE_INTERRUPT(207) \
 627         DECLARE_INTERRUPT(208) \
 628         DECLARE_INTERRUPT(209) \
 629         DECLARE_INTERRUPT(210) \
 630         DECLARE_INTERRUPT(211) \
 631         DECLARE_INTERRUPT(212) \
 632         DECLARE_INTERRUPT(213) \
 633         DECLARE_INTERRUPT(214) \
 634         DECLARE_INTERRUPT(215) \
 635         DECLARE_INTERRUPT(216) \
 636         DECLARE_INTERRUPT(217) \
 637         DECLARE_INTERRUPT(218) \
 638         DECLARE_INTERRUPT(219) \
 639         DECLARE_INTERRUPT(220) \
 640         DECLARE_INTERRUPT(221) \
 641         DECLARE_INTERRUPT(222) \
 642         DECLARE_INTERRUPT(223) \
 643         DECLARE_INTERRUPT(224) \
 644         DECLARE_INTERRUPT(225) \
 645         DECLARE_INTERRUPT(226) \
 646         DECLARE_INTERRUPT(227) \
 647         DECLARE_INTERRUPT(228) \
 648         DECLARE_INTERRUPT(229) \
 649         DECLARE_INTERRUPT(230) \
 650         DECLARE_INTERRUPT(231) \
 651         DECLARE_INTERRUPT(232) \
 652         DECLARE_INTERRUPT(233) \
 653         DECLARE_INTERRUPT(234) \
 654         DECLARE_INTERRUPT(235) \
 655         DECLARE_INTERRUPT(236) \
 656         DECLARE_INTERRUPT(237) \
 657         DECLARE_INTERRUPT(238) \
 658         DECLARE_INTERRUPT(239) \
 659         DECLARE_INTERRUPT(240) \
 660         DECLARE_INTERRUPT(241) \
 661         DECLARE_INTERRUPT(242) \
 662         DECLARE_INTERRUPT(243) \
 663         DECLARE_INTERRUPT(244) \
 664         DECLARE_INTERRUPT(245) \
 665         DECLARE_INTERRUPT(246) \
 666         DECLARE_INTERRUPT(247) \
 667         DECLARE_INTERRUPT(248) \
 668         DECLARE_INTERRUPT(249) \
 669         DECLARE_INTERRUPT(250) \
 670         DECLARE_INTERRUPT(251) \
 671         DECLARE_INTERRUPT(252) \
 672         DECLARE_INTERRUPT(253) \
 673         DECLARE_INTERRUPT(254) \
 674         DECLARE_INTERRUPT(255));