arch/m68k/cpu/mcf5445x/cpu_init.c

   1 /*
   2  *
   3  * (C) Copyright 2000-2003
   4  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5  *
   6  * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
   7  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <common.h>
  29 #include <watchdog.h>
  30 #include <asm/immap.h>
  31 #include <asm/processor.h>
  32 #include <asm/rtc.h>
  33 #include <asm/io.h>
  34 #include <linux/compiler.h>
  35
  36 #if defined(CONFIG_CMD_NET)
  37 #include <config.h>
  38 #include <net.h>
  39 #include <asm/fec.h>
  40 #endif
  41
  42 void init_fbcs(void)
  43 {
  44         fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
  45
  46 #if !defined(CONFIG_SERIAL_BOOT)
  47 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
  48         out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
  49         out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
  50         out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
  51 #endif
  52 #endif
  53
  54 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
  55         /* Latch chipselect */
  56         out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
  57         out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
  58         out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
  59 #endif
  60
  61 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
  62         out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
  63         out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
  64         out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
  65 #endif
  66
  67 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
  68         out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
  69         out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
  70         out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
  71 #endif
  72
  73 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
  74         out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
  75         out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
  76         out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
  77 #endif
  78
  79 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
  80         out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
  81         out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
  82         out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
  83 #endif
  84 }
  85
  86 /*
  87  * Breath some life into the CPU...
  88  *
  89  * Set up the memory map,
  90  * initialize a bunch of registers,
  91  * initialize the UPM's
  92  */
  93 void cpu_init_f(void)
  94 {
  95         gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  96
  97 #ifdef CONFIG_MCF5441x
  98         scm_t *scm = (scm_t *) MMAP_SCM;
  99         pm_t *pm = (pm_t *) MMAP_PM;
 100
 101         /* Disable Switch */
 102         *(unsigned long *)(MMAP_L2_SW0 + 0x00000024) = 0;
 103
 104         /* Disable core watchdog */
 105         out_be16(&scm->cwcr, 0);
 106         out_8(&gpio->par_fbctl,
 107                 GPIO_PAR_FBCTL_ALE_FB_ALE | GPIO_PAR_FBCTL_OE_FB_OE |
 108                 GPIO_PAR_FBCTL_FBCLK | GPIO_PAR_FBCTL_RW |
 109                 GPIO_PAR_FBCTL_TA_TA);
 110         out_8(&gpio->par_be,
 111                 GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
 112                 GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
 113
 114         /* eDMA */
 115         out_8(&pm->pmcr0, 17);
 116
 117         /* INTR0 - INTR2 */
 118         out_8(&pm->pmcr0, 18);
 119         out_8(&pm->pmcr0, 19);
 120         out_8(&pm->pmcr0, 20);
 121
 122         /* I2C */
 123         out_8(&pm->pmcr0, 22);
 124         out_8(&pm->pmcr1, 4);
 125         out_8(&pm->pmcr1, 7);
 126
 127         /* DTMR0 - DTMR3*/
 128         out_8(&pm->pmcr0, 28);
 129         out_8(&pm->pmcr0, 29);
 130         out_8(&pm->pmcr0, 30);
 131         out_8(&pm->pmcr0, 31);
 132
 133         /* PIT0 - PIT3 */
 134         out_8(&pm->pmcr0, 32);
 135         out_8(&pm->pmcr0, 33);
 136         out_8(&pm->pmcr0, 34);
 137         out_8(&pm->pmcr0, 35);
 138
 139         /* Edge Port */
 140         out_8(&pm->pmcr0, 36);
 141         out_8(&pm->pmcr0, 37);
 142
 143         /* USB OTG */
 144         out_8(&pm->pmcr0, 44);
 145         /* USB Host */
 146         out_8(&pm->pmcr0, 45);
 147
 148         /* ESDHC */
 149         out_8(&pm->pmcr0, 51);
 150
 151         /* ENET0 - ENET1 */
 152         out_8(&pm->pmcr0, 53);
 153         out_8(&pm->pmcr0, 54);
 154
 155         /* NAND */
 156         out_8(&pm->pmcr0, 63);
 157
 158 #ifdef CONFIG_SYS_I2C_0
 159         out_8(&gpio->par_cani2c, 0xF0);
 160         /* I2C0 pull up */
 161         out_be16(&gpio->pcr_b, 0x003C);
 162         /* I2C0 max speed */
 163         out_8(&gpio->srcr_cani2c, 0x03);
 164 #endif
 165 #ifdef CONFIG_SYS_I2C_2
 166         /* I2C2 */
 167         out_8(&gpio->par_ssi0h, 0xA0);
 168         /* I2C2, UART7 */
 169         out_8(&gpio->par_ssi0h, 0xA8);
 170         /* UART7 */
 171         out_8(&gpio->par_ssi0l, 0x2);
 172         /* UART8, UART9 */
 173         out_8(&gpio->par_cani2c, 0xAA);
 174         /* UART4, UART0 */
 175         out_8(&gpio->par_uart0, 0xAF);
 176         /* UART5, UART1 */
 177         out_8(&gpio->par_uart1, 0xAF);
 178         /* UART6, UART2 */
 179         out_8(&gpio->par_uart2, 0xAF);
 180         /* I2C2 pull up */
 181         out_be16(&gpio->pcr_h, 0xF000);
 182 #endif
 183 #ifdef CONFIG_SYS_I2C_5
 184         /* I2C5 */
 185         out_8(&gpio->par_uart1, 0x0A);
 186         /* I2C5 pull up */
 187         out_be16(&gpio->pcr_e, 0x0003);
 188         out_be16(&gpio->pcr_f, 0xC000);
 189 #endif
 190
 191         /* Lowest slew rate for UART0,1,2 */
 192         out_8(&gpio->srcr_uart, 0x00);
 193 #endif          /* CONFIG_MCF5441x */
 194
 195 #ifdef CONFIG_MCF5445x
 196         scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
 197
 198         out_be32(&scm1->mpr, 0x77777777);
 199         out_be32(&scm1->pacra, 0);
 200         out_be32(&scm1->pacrb, 0);
 201         out_be32(&scm1->pacrc, 0);
 202         out_be32(&scm1->pacrd, 0);
 203         out_be32(&scm1->pacre, 0);
 204         out_be32(&scm1->pacrf, 0);
 205         out_be32(&scm1->pacrg, 0);
 206
 207         /* FlexBus */
 208         out_8(&gpio->par_be,
 209                 GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
 210                 GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
 211         out_8(&gpio->par_fbctl,
 212                 GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
 213                 GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
 214
 215 #ifdef CONFIG_SYS_FSL_I2C
 216         out_be16(&gpio->par_feci2c,
 217                 GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
 218 #endif
 219 #endif          /* CONFIG_MCF5445x */
 220
 221         /* FlexBus Chipselect */
 222         init_fbcs();
 223
 224         /*
 225          * now the flash base address is no longer at 0 (Newer ColdFire family
 226          * boot at address 0 instead of 0xFFnn_nnnn). The vector table must
 227          * also move to the new location.
 228          */
 229         if (CONFIG_SYS_CS0_BASE != 0)
 230                 setvbr(CONFIG_SYS_CS0_BASE);
 231
 232         icache_enable();
 233 }
 234
 235 /*
 236  * initialize higher level parts of CPU like timers
 237  */
 238 int cpu_init_r(void)
 239 {
 240 #ifdef CONFIG_MCFRTC
 241         rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
 242         rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
 243
 244         out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
 245         out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
 246 #endif
 247
 248         return (0);
 249 }
 250
 251 void uart_port_conf(int port)
 252 {
 253         gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 254 #ifdef CONFIG_MCF5441x
 255         pm_t *pm = (pm_t *) MMAP_PM;
 256 #endif
 257
 258         /* Setup Ports: */
 259         switch (port) {
 260 #ifdef CONFIG_MCF5441x
 261         case 0:
 262                 /* UART0 */
 263                 out_8(&pm->pmcr0, 24);
 264                 clrbits_8(&gpio->par_uart0,
 265                         ~(GPIO_PAR_UART0_U0RXD_MASK | GPIO_PAR_UART0_U0TXD_MASK));
 266                 setbits_8(&gpio->par_uart0,
 267                         GPIO_PAR_UART0_U0RXD_U0RXD | GPIO_PAR_UART0_U0TXD_U0TXD);
 268                 break;
 269         case 1:
 270                 /* UART1 */
 271                 out_8(&pm->pmcr0, 25);
 272                 clrbits_8(&gpio->par_uart1,
 273                         ~(GPIO_PAR_UART1_U1RXD_MASK | GPIO_PAR_UART1_U1TXD_MASK));
 274                 setbits_8(&gpio->par_uart1,
 275                         GPIO_PAR_UART1_U1RXD_U1RXD | GPIO_PAR_UART1_U1TXD_U1TXD);
 276                 break;
 277         case 2:
 278                 /* UART2 */
 279                 out_8(&pm->pmcr0, 26);
 280                 clrbits_8(&gpio->par_uart2,
 281                         ~(GPIO_PAR_UART2_U2RXD_MASK | GPIO_PAR_UART2_U2TXD_MASK));
 282                 setbits_8(&gpio->par_uart2,
 283                         GPIO_PAR_UART2_U2RXD_U2RXD | GPIO_PAR_UART2_U2TXD_U2TXD);
 284                 break;
 285         case 3:
 286                 /* UART3 */
 287                 out_8(&pm->pmcr0, 27);
 288                 clrbits_8(&gpio->par_dspi0,
 289                         ~(GPIO_PAR_DSPI0_SIN_MASK | GPIO_PAR_DSPI0_SOUT_MASK));
 290                 setbits_8(&gpio->par_dspi0,
 291                         GPIO_PAR_DSPI0_SIN_U3RXD | GPIO_PAR_DSPI0_SOUT_U3TXD);
 292                 break;
 293         case 4:
 294                 /* UART4 */
 295                 out_8(&pm->pmcr1, 24);
 296                 clrbits_8(&gpio->par_uart0,
 297                         ~(GPIO_PAR_UART0_U0CTS_MASK | GPIO_PAR_UART0_U0RTS_MASK));
 298                 setbits_8(&gpio->par_uart0,
 299                         GPIO_PAR_UART0_U0CTS_U4TXD | GPIO_PAR_UART0_U0RTS_U4RXD);
 300                 break;
 301         case 5:
 302                 /* UART5 */
 303                 out_8(&pm->pmcr1, 25);
 304                 clrbits_8(&gpio->par_uart1,
 305                         ~(GPIO_PAR_UART1_U1CTS_MASK | GPIO_PAR_UART1_U1RTS_MASK));
 306                 setbits_8(&gpio->par_uart1,
 307                         GPIO_PAR_UART1_U1CTS_U5TXD | GPIO_PAR_UART1_U1RTS_U5RXD);
 308                 break;
 309         case 6:
 310                 /* UART6 */
 311                 out_8(&pm->pmcr1, 26);
 312                 clrbits_8(&gpio->par_uart2,
 313                         ~(GPIO_PAR_UART2_U2CTS_MASK | GPIO_PAR_UART2_U2RTS_MASK));
 314                 setbits_8(&gpio->par_uart2,
 315                         GPIO_PAR_UART2_U2CTS_U6TXD | GPIO_PAR_UART2_U2RTS_U6RXD);
 316                 break;
 317         case 7:
 318                 /* UART7 */
 319                 out_8(&pm->pmcr1, 27);
 320                 clrbits_8(&gpio->par_ssi0h, ~GPIO_PAR_SSI0H_RXD_MASK);
 321                 clrbits_8(&gpio->par_ssi0l, ~GPIO_PAR_SSI0L_BCLK_MASK);
 322                 setbits_8(&gpio->par_ssi0h, GPIO_PAR_SSI0H_FS_U7TXD);
 323                 setbits_8(&gpio->par_ssi0l, GPIO_PAR_SSI0L_BCLK_U7RXD);
 324                 break;
 325         case 8:
 326                 /* UART8 */
 327                 out_8(&pm->pmcr0, 28);
 328                 clrbits_8(&gpio->par_cani2c,
 329                         ~(GPIO_PAR_CANI2C_I2C0SCL_MASK | GPIO_PAR_CANI2C_I2C0SDA_MASK));
 330                 setbits_8(&gpio->par_cani2c,
 331                         GPIO_PAR_CANI2C_I2C0SCL_U8TXD | GPIO_PAR_CANI2C_I2C0SDA_U8RXD);
 332                 break;
 333         case 9:
 334                 /* UART9 */
 335                 out_8(&pm->pmcr1, 29);
 336                 clrbits_8(&gpio->par_cani2c,
 337                         ~(GPIO_PAR_CANI2C_CAN1TX_MASK | GPIO_PAR_CANI2C_CAN1RX_MASK));
 338                 setbits_8(&gpio->par_cani2c,
 339                         GPIO_PAR_CANI2C_CAN1TX_U9TXD | GPIO_PAR_CANI2C_CAN1RX_U9RXD);
 340                 break;
 341 #endif
 342 #ifdef CONFIG_MCF5445x
 343         case 0:
 344                 clrbits_8(&gpio->par_uart,
 345                         GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
 346                 setbits_8(&gpio->par_uart,
 347                         GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
 348                 break;
 349         case 1:
 350 #ifdef CONFIG_SYS_UART1_PRI_GPIO
 351                 clrbits_8(&gpio->par_uart,
 352                         GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
 353                 setbits_8(&gpio->par_uart,
 354                         GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
 355 #elif defined(CONFIG_SYS_UART1_ALT1_GPIO)
 356                 clrbits_be16(&gpio->par_ssi,
 357                         ~(GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK));
 358                 setbits_be16(&gpio->par_ssi,
 359                         GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD);
 360 #endif
 361                 break;
 362         case 2:
 363 #if defined(CONFIG_SYS_UART2_ALT1_GPIO)
 364                 clrbits_8(&gpio->par_timer,
 365                         ~(GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK));
 366                 setbits_8(&gpio->par_timer,
 367                         GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD);
 368 #elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
 369                 clrbits_8(&gpio->par_timer,
 370                         ~(GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK));
 371                 setbits_8(&gpio->par_timer,
 372                         GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
 373 #endif
 374                 break;
 375 #endif  /* CONFIG_MCF5445x */
 376         }
 377 }
 378
 379 #if defined(CONFIG_CMD_NET)
 380 int fecpin_setclear(struct eth_device *dev, int setclear)
 381 {
 382         gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 383         struct fec_info_s *info = (struct fec_info_s *)dev->priv;
 384
 385 #ifdef CONFIG_MCF5445x
 386         if (setclear) {
 387 #ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
 388                 if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
 389                         setbits_be16(&gpio->par_feci2c,
 390                                 GPIO_PAR_FECI2C_MDC0_MDC0 |
 391                                 GPIO_PAR_FECI2C_MDIO0_MDIO0);
 392                 else
 393                         setbits_be16(&gpio->par_feci2c,
 394                                 GPIO_PAR_FECI2C_MDC1_MDC1 |
 395                                 GPIO_PAR_FECI2C_MDIO1_MDIO1);
 396 #else
 397                 setbits_be16(&gpio->par_feci2c,
 398                         GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
 399 #endif
 400
 401                 if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
 402                         setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO);
 403                 else
 404                         setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA);
 405         } else {
 406                 clrbits_be16(&gpio->par_feci2c,
 407                         GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
 408
 409                 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
 410 #ifdef CONFIG_SYS_FEC_FULL_MII
 411                         setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII);
 412 #else
 413                         clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC0_UNMASK);
 414 #endif
 415                 } else {
 416 #ifdef CONFIG_SYS_FEC_FULL_MII
 417                         setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_MII);
 418 #else
 419                         clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC1_UNMASK);
 420 #endif
 421                 }
 422         }
 423 #endif  /* CONFIG_MCF5445x */
 424
 425 #ifdef CONFIG_MCF5441x
 426         if (setclear) {
 427                 out_8(&gpio->par_fec, 0x03);
 428                 out_8(&gpio->srcr_fec, 0x0F);
 429                 clrsetbits_8(&gpio->par_simp0h, ~GPIO_PAR_SIMP0H_DAT_MASK,
 430                         GPIO_PAR_SIMP0H_DAT_GPIO);
 431                 clrsetbits_8(&gpio->pddr_g, ~GPIO_PDDR_G4_MASK,
 432                         GPIO_PDDR_G4_OUTPUT);
 433                 clrbits_8(&gpio->podr_g, ~GPIO_PODR_G4_MASK);
 434
 435         } else
 436                 clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC_MASK);
 437 #endif
 438         return 0;
 439 }
 440 #endif
 441
 442 #ifdef CONFIG_CF_DSPI
 443 void cfspi_port_conf(void)
 444 {
 445         gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 446
 447 #ifdef CONFIG_MCF5445x
 448         out_8(&gpio->par_dspi,
 449                 GPIO_PAR_DSPI_SIN_SIN |
 450                 GPIO_PAR_DSPI_SOUT_SOUT |
 451                 GPIO_PAR_DSPI_SCK_SCK);
 452 #endif
 453
 454 #ifdef CONFIG_MCF5441x
 455         pm_t *pm = (pm_t *) MMAP_PM;
 456
 457         out_8(&gpio->par_dspi0,
 458                 GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
 459                 GPIO_PAR_DSPI0_SCK_DSPI0SCK);
 460         out_8(&gpio->srcr_dspiow, 3);
 461
 462         /* DSPI0 */
 463         out_8(&pm->pmcr0, 23);
 464 #endif
 465 }
 466
 467 int cfspi_claim_bus(uint bus, uint cs)
 468 {
 469         dspi_t *dspi = (dspi_t *) MMAP_DSPI;
 470         gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 471
 472         if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
 473                 return -1;
 474
 475         /* Clear FIFO and resume transfer */
 476         clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
 477
 478 #ifdef CONFIG_MCF5445x
 479         switch (cs) {
 480         case 0:
 481                 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
 482                 setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
 483                 break;
 484         case 1:
 485                 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
 486                 setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
 487                 break;
 488         case 2:
 489                 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
 490                 setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
 491                 break;
 492         case 3:
 493                 clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
 494                 setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
 495                 break;
 496         case 5:
 497                 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
 498                 setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
 499                 break;
 500         }
 501 #endif
 502
 503 #ifdef CONFIG_MCF5441x
 504         switch (cs) {
 505         case 0:
 506                 clrbits_8(&gpio->par_dspi0, ~GPIO_PAR_DSPI0_PCS0_MASK);
 507                 setbits_8(&gpio->par_dspi0, GPIO_PAR_DSPI0_PCS0_DSPI0PCS0);
 508                 break;
 509         case 1:
 510                 clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
 511                 setbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
 512                 break;
 513         }
 514 #endif
 515
 516         return 0;
 517 }
 518
 519 void cfspi_release_bus(uint bus, uint cs)
 520 {
 521         dspi_t *dspi = (dspi_t *) MMAP_DSPI;
 522         gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 523
 524         /* Clear FIFO */
 525         clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
 526
 527 #ifdef CONFIG_MCF5445x
 528         switch (cs) {
 529         case 0:
 530                 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
 531                 break;
 532         case 1:
 533                 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
 534                 break;
 535         case 2:
 536                 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
 537                 break;
 538         case 3:
 539                 clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
 540                 break;
 541         case 5:
 542                 clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
 543                 break;
 544         }
 545 #endif
 546
 547 #ifdef CONFIG_MCF5441x
 548         if (cs == 1)
 549                 clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
 550 #endif
 551 }
 552 #endif