2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
5 * Copyright 2010-2012 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm-offsets.h>
14 #include <timestamp.h>
16 #include <asm/cache.h>
22 move.w #0x2700,%sr; /* disable intrs */ \
23 subl #60,%sp; /* space for 15 regs */ \
24 moveml %d0-%d7/%a0-%a6,%sp@;
27 moveml %sp@,%d0-%d7/%a0-%a6; \
28 addl #60,%sp; /* space for 15 regs */ \
31 #if defined(CONFIG_SERIAL_BOOT)
32 #define ASM_DRAMINIT (asm_dram_init - CONFIG_SYS_TEXT_BASE + \
33 CONFIG_SYS_INIT_RAM_ADDR)
34 #define ASM_DRAMINIT_N (asm_dram_init - CONFIG_SYS_TEXT_BASE)
35 #define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + \
36 CONFIG_SYS_INIT_RAM_ADDR)
42 * Vector table. This is used for initial platform startup.
43 * These vectors are to catch any un-intended traps.
46 #if defined(CONFIG_SERIAL_BOOT)
48 INITSP: .long 0 /* Initial SP */
50 INITPC: .long ASM_DRAMINIT /* Initial PC */
52 #ifdef CONFIG_SYS_NAND_BOOT
53 INITPC: .long ASM_DRAMINIT_N /* Initial PC */
58 INITSP: .long 0 /* Initial SP */
59 INITPC: .long _START /* Initial PC */
64 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
65 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
69 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
72 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
74 #if !defined(CONFIG_SERIAL_BOOT)
78 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
79 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
83 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
84 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
87 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
88 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
90 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
91 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
92 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
93 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
94 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
97 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
98 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
99 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
100 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
101 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
102 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
103 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
104 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
107 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
108 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
109 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
110 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
111 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
112 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
113 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
114 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
117 #if defined(CONFIG_SERIAL_BOOT)
118 /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
120 .long 0x00000000 /* checksum, not yet implemented */
121 .long 0x00040000 /* image length */
122 .long CONFIG_SYS_TEXT_BASE /* image to be relocated at */
125 move.w #0x2700,%sr /* Mask off Interrupt */
127 #ifdef CONFIG_SYS_NAND_BOOT
128 /* for assembly stack */
129 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
132 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
137 move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0
140 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
143 /* initialize general use internal ram */
145 move.l #(ICACHE_STATUS), %a1 /* icache */
146 move.l #(DCACHE_STATUS), %a2 /* dcache */
150 /* invalidate and disable cache */
151 move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
152 movec %d0, %CACR /* Invalidate cache */
159 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
162 /* Must disable global address */
163 move.l #0xFC008000, %a1
164 move.l #(CONFIG_SYS_CS0_BASE), (%a1)
165 move.l #0xFC008008, %a1
166 move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
167 move.l #0xFC008004, %a1
168 move.l #(CONFIG_SYS_CS0_MASK), (%a1)
169 #endif /* CONFIG_CF_SBF */
171 #ifdef CONFIG_MCF5441x
172 /* TC: enable all peripherals,
173 in the future only enable certain peripherals */
174 move.l #0xFC04002D, %a1
176 #if defined(CONFIG_CF_SBF)
177 move.b #23, (%a1) /* dspi */
179 move.b #46, (%a1) /* DDR */
182 move.l #0xEC094060, %a1
185 /* use vco instead of cpu*2 clock for ddr clock */
186 move.l #0xEC09001A, %a1
187 move.w #0xE01D, (%a1)
190 move.l #0xFC0B8180, %a1
191 move.l #0x00000000, (%a1)
192 move.l #0x40000000, (%a1)
194 move.l #0xFC0B81AC, %a1
195 move.l #0x01030203, (%a1)
197 move.l #0xFC0B8000, %a1
198 move.l #0x01010101, (%a1)+ /* 0x00 */
199 move.l #0x00000101, (%a1)+ /* 0x04 */
200 move.l #0x01010100, (%a1)+ /* 0x08 */
201 move.l #0x01010000, (%a1)+ /* 0x0C */
202 move.l #0x00010101, (%a1)+ /* 0x10 */
203 move.l #0xFC0B8018, %a1
204 move.l #0x00010100, (%a1)+ /* 0x18 */
205 move.l #0x00000001, (%a1)+ /* 0x1C */
206 move.l #0x01000001, (%a1)+ /* 0x20 */
207 move.l #0x00000100, (%a1)+ /* 0x24 */
208 move.l #0x00010001, (%a1)+ /* 0x28 */
209 move.l #0x00000200, (%a1)+ /* 0x2C */
210 move.l #0x01000002, (%a1)+ /* 0x30 */
211 move.l #0x00000000, (%a1)+ /* 0x34 */
212 move.l #0x00000100, (%a1)+ /* 0x38 */
213 move.l #0x02000100, (%a1)+ /* 0x3C */
214 move.l #0x02000407, (%a1)+ /* 0x40 */
215 move.l #0x02030007, (%a1)+ /* 0x44 */
216 move.l #0x02000100, (%a1)+ /* 0x48 */
217 move.l #0x0A030203, (%a1)+ /* 0x4C */
218 move.l #0x00020708, (%a1)+ /* 0x50 */
219 move.l #0x00050008, (%a1)+ /* 0x54 */
220 move.l #0x04030002, (%a1)+ /* 0x58 */
221 move.l #0x00000004, (%a1)+ /* 0x5C */
222 move.l #0x020A0000, (%a1)+ /* 0x60 */
223 move.l #0x0C00000E, (%a1)+ /* 0x64 */
224 move.l #0x00002004, (%a1)+ /* 0x68 */
225 move.l #0x00000000, (%a1)+ /* 0x6C */
226 move.l #0x00100010, (%a1)+ /* 0x70 */
227 move.l #0x00100010, (%a1)+ /* 0x74 */
228 move.l #0x00000000, (%a1)+ /* 0x78 */
229 move.l #0x07990000, (%a1)+ /* 0x7C */
230 move.l #0xFC0B80A0, %a1
231 move.l #0x00000000, (%a1)+ /* 0xA0 */
232 move.l #0x00C80064, (%a1)+ /* 0xA4 */
233 move.l #0x44520002, (%a1)+ /* 0xA8 */
234 move.l #0x00C80023, (%a1)+ /* 0xAC */
235 move.l #0xFC0B80B4, %a1
236 move.l #0x0000C350, (%a1) /* 0xB4 */
237 move.l #0xFC0B80E0, %a1
238 move.l #0x04000000, (%a1)+ /* 0xE0 */
239 move.l #0x03000304, (%a1)+ /* 0xE4 */
240 move.l #0x40040000, (%a1)+ /* 0xE8 */
241 move.l #0xC0004004, (%a1)+ /* 0xEC */
242 move.l #0x0642C000, (%a1)+ /* 0xF0 */
243 move.l #0x00000642, (%a1)+ /* 0xF4 */
244 move.l #0xFC0B8024, %a1
246 move.l #0x01000100, (%a1) /* 0x24 */
250 #endif /* CONFIG_MCF5441x */
252 #ifdef CONFIG_MCF5445x
253 /* Dram Initialization a1, a2, and d0 */
255 move.l #0xFC0A4074, %a1
256 move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
259 /* SDRAM Chip 0 and 1 */
260 move.l #0xFC0B8110, %a1
261 move.l #0xFC0B8114, %a2
263 /* calculate the size */
265 move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
266 #ifdef CONFIG_SYS_SDRAM_BASE1
275 #ifdef CONFIG_SYS_NAND_BOOT
276 beq asm_nand_chk_status
278 /* SDRAM Chip 0 and 1 */
279 move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
281 #ifdef CONFIG_SYS_SDRAM_BASE1
282 move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
287 /* dram cfg1 and cfg2 */
288 move.l #0xFC0B8008, %a1
289 move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
291 move.l #0xFC0B800C, %a2
292 move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
295 move.l #0xFC0B8000, %a1 /* Mode */
296 move.l #0xFC0B8004, %a2 /* Ctrl */
299 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
302 #ifdef CONFIG_M54455EVB
304 move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
306 move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
314 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
317 /* Perform two refresh cycles */
318 move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
324 #ifdef CONFIG_M54455EVB
325 move.l #(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1)
327 #elif defined(CONFIG_M54451EVB)
329 move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
331 move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
337 move.l #(CONFIG_SYS_SDRAM_CTRL), %d1
338 and.l #0x7FFFFFFF, %d1
339 #ifdef CONFIG_M54455EVB
340 or.l #0x10000C00, %d1
341 #elif defined(CONFIG_M54451EVB)
342 or.l #0x10000C00, %d1
349 #endif /* CONFIG_MCF5445x */
353 * DSPI Initialization
354 * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
360 /* Enable pins for DSPI mode - chip-selects are enabled later */
362 #ifdef CONFIG_MCF5441x
363 move.l #0xEC09404E, %a1
364 move.l #0xEC09404F, %a2
369 #ifdef CONFIG_MCF5445x
370 move.l #0xFC0A4063, %a0
373 /* Configure DSPI module */
374 move.l #0xFC05C000, %a0
375 move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
377 move.l #0xFC05C00C, %a0
378 #ifdef CONFIG_MCF5441x
379 move.l #0x3E000016, (%a0)
381 #ifdef CONFIG_MCF5445x
382 move.l #0x3E000011, (%a0)
385 move.l #0xFC05C034, %a2 /* dtfr */
386 move.l #0xFC05C03B, %a3 /* drfr */
388 move.l #(ASM_SBF_IMG_HDR + 4), %a1
392 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
393 move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4
395 move.l #0xFC05C02C, %a1 /* dspi status */
397 /* Issue commands and address */
398 move.l #0x8002000B, %d2 /* Fast Read Cmd */
399 jsr asm_dspi_wr_status
400 jsr asm_dspi_rd_status
402 move.l #0x80020000, %d2 /* Address byte 2 */
403 jsr asm_dspi_wr_status
404 jsr asm_dspi_rd_status
406 move.l #0x80020000, %d2 /* Address byte 1 */
407 jsr asm_dspi_wr_status
408 jsr asm_dspi_rd_status
410 move.l #0x80020000, %d2 /* Address byte 0 */
411 jsr asm_dspi_wr_status
412 jsr asm_dspi_rd_status
414 move.l #0x80020000, %d2 /* Dummy Wr and Rd */
415 jsr asm_dspi_wr_status
416 jsr asm_dspi_rd_status
418 /* Transfer serial boot header to sram */
420 move.l #0x80020000, %d2
421 jsr asm_dspi_wr_status
422 jsr asm_dspi_rd_status
424 move.b %d1, (%a0) /* read, copy to dst */
426 add.l #1, %a0 /* inc dst by 1 */
427 sub.l #1, %d4 /* dec cnt by 1 */
428 bne asm_dspi_rd_loop1
430 /* Transfer u-boot from serial flash to memory */
432 move.l #0x80020000, %d2
433 jsr asm_dspi_wr_status
434 jsr asm_dspi_rd_status
436 move.b %d1, (%a4) /* read, copy to dst */
438 add.l #1, %a4 /* inc dst by 1 */
439 sub.l #1, %d5 /* dec cnt by 1 */
440 bne asm_dspi_rd_loop2
442 move.l #0x00020000, %d2 /* Terminate */
443 jsr asm_dspi_wr_status
444 jsr asm_dspi_rd_status
446 /* jump to memory and execute */
447 move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0
451 move.l (%a1), %d0 /* status */
452 and.l #0x0000F000, %d0
453 cmp.l #0x00003000, %d0
454 bgt asm_dspi_wr_status
460 move.l (%a1), %d0 /* status */
461 and.l #0x000000F0, %d0
464 beq asm_dspi_rd_status
468 #endif /* CONFIG_CF_SBF */
470 #ifdef CONFIG_SYS_NAND_BOOT
471 /* copy 4 boot pages to dram as soon as possible */
472 /* each page is 996 bytes (1056 total with 60 ECC bytes */
473 move.l #0x00000000, %a1 /* src */
474 move.l #CONFIG_SYS_TEXT_BASE, %a2 /* dst */
475 move.l #0x3E0, %d0 /* sz in long */
478 move.l (%a1)+, (%a2)+
480 bne asm_boot_nand_copy
482 /* jump to memory and execute */
483 move.l #(asm_nand_init), %a0
487 /* exit nand boot-mode */
488 move.l #0xFC0FFF30, %a1
489 or.l #0x00000040, %d1
492 /* initialize general use internal ram */
494 move.l #(CACR_STATUS), %a1 /* CACR */
495 move.l #(ICACHE_STATUS), %a2 /* icache */
496 move.l #(DCACHE_STATUS), %a3 /* dcache */
501 /* invalidate and disable cache */
502 move.l #0x01004100, %d0 /* Invalidate cache cmd */
503 movec %d0, %CACR /* Invalidate cache */
510 /* Must disable global address */
511 move.l #0xFC008000, %a1
512 move.l #(CONFIG_SYS_CS0_BASE), (%a1)
513 move.l #0xFC008008, %a1
514 move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
515 move.l #0xFC008004, %a1
516 move.l #(CONFIG_SYS_CS0_MASK), (%a1)
518 /* NAND port configuration */
519 move.l #0xEC094048, %a1
525 move.l #0xFC0FFF38, %a1 /* isr */
526 move.l #0x000e0000, (%a1)
527 move.l #0xFC0FFF08, %a2
528 move.l #0x00000000, (%a2)+ /* car */
529 move.l #0x11000000, (%a2)+ /* rar */
530 move.l #0x00000000, (%a2)+ /* rpt */
531 move.l #0x00000000, (%a2)+ /* rai */
532 move.l #0xFC0FFF2c, %a2 /* cfg */
533 move.l #0x00000000, (%a2)+ /* secsz */
534 move.l #0x000e0681, (%a2)+
535 move.l #0xFC0FFF04, %a2 /* cmd2 */
536 move.l #0xFF404001, (%a2)
537 move.l #0x000e0000, (%a1)
543 move.l #0xFC0FFF00, %a1
544 move.l #0x30700000, (%a1)+ /* cmd1 */
545 move.l #0x007EF000, (%a1)+ /* cmd2 */
547 move.l #0xFC0FFF2C, %a1
548 move.l #0x00000841, (%a1)+ /* secsz */
549 move.l #0x000e0681, (%a1)+ /* cfg */
551 move.l #100, %d4 /* 100 pages ~200KB */
552 move.l #4, %d2 /* start at 4 */
553 move.l #0xFC0FFF04, %a0 /* cmd2 */
554 move.l #0xFC0FFF0C, %a1 /* rar */
555 move.l #(CONFIG_SYS_TEXT_BASE + 0xF80), %a2
558 move.l #0x11000000, %d0 /* rar */
563 move.l (%a0), %d0 /* cmd2 */
571 move.l #0xFC0FFF38, %a4 /* isr */
573 and.l #0x40000000, %d0
575 beq asm_nand_chk_status
577 move.l #0xFC0FFF38, %a4 /* isr */
579 or.l #0x000E0000, %d0
583 move.l #0xFC0FC000, %a3 /* buf 1 */
585 move.l (%a3)+, (%a2)+
592 /* jump to memory and execute */
593 move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0
596 #endif /* CONFIG_SYS_NAND_BOOT */
603 #endif /* CONFIG_CF_SBF || CONFIG_NAND_U_BOOT */
609 #if !defined(CONFIG_SERIAL_BOOT)
612 move.w #0x2700,%sr /* Mask off Interrupt */
614 /* Set vector base register at the beginning of the Flash */
615 move.l #CONFIG_SYS_FLASH_BASE, %d0
618 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
621 /* initialize general use internal ram */
623 move.l #(ICACHE_STATUS), %a1 /* icache */
624 move.l #(DCACHE_STATUS), %a2 /* dcache */
628 /* invalidate and disable cache */
629 move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
630 movec %d0, %CACR /* Invalidate cache */
637 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
641 /* put relocation table address to a5 */
642 move.l #__got_start, %a5
644 /* setup stack initially on top of internal static ram */
645 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
648 * if configured, malloc_f arena will be reserved first,
649 * then (and always) gd struct space will be reserved
652 move.l #board_init_f_alloc_reserve, %a1
655 /* update stack and frame-pointers */
659 /* initialize reserved area */
661 move.l #board_init_f_init_reserve, %a1
664 /* run low-level CPU init code (from flash) */
665 move.l #cpu_init_f, %a1
668 /* run low-level board init code (from flash) */
670 move.l #board_init_f, %a1
673 /* board_init_f() does not return */
675 /******************************************************************************/
678 * void relocate_code (addr_sp, gd, addr_moni)
680 * This "function" does not return, instead it continues in RAM
681 * after relocating the monitor code.
685 * r5 = length in bytes
691 move.l 8(%a6), %sp /* set new stack pointer */
693 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
694 move.l 16(%a6), %a0 /* Save copy of Destination Address */
696 move.l #CONFIG_SYS_MONITOR_BASE, %a1
697 move.l #__init_end, %a2
700 /* copy the code to RAM */
702 move.l (%a1)+, (%a3)+
707 * We are done. Do not return, instead branch to second part of board
708 * initialization, now running from RAM.
711 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
718 * Now clear BSS segment
721 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
723 add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
730 * fix got table in RAM
733 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
734 move.l %a1,%a5 /* fix got pointer register a5 */
737 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
747 /* calculate relative jump to board_init_r in ram */
749 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
751 /* set parameters for board_init_r */
752 move.l %a0,-(%sp) /* dest_addr */
753 move.l %d0,-(%sp) /* gd */
756 /******************************************************************************/
779 /******************************************************************************/
781 .globl version_string
783 .ascii U_BOOT_VERSION_STRING, "\0"