arch/m68k/cpu/mcf547x_8x/cpu_init.c

   1 /*
   2  *
   3  * (C) Copyright 2000-2003
   4  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5  *
   6  * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
   7  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <MCD_dma.h>
  14 #include <asm/immap.h>
  15 #include <asm/io.h>
  16
  17 #if defined(CONFIG_CMD_NET)
  18 #include <config.h>
  19 #include <net.h>
  20 #include <asm/fsl_mcdmafec.h>
  21 #endif
  22
  23 /*
  24  * Breath some life into the CPU...
  25  *
  26  * Set up the memory map,
  27  * initialize a bunch of registers,
  28  * initialize the UPM's
  29  */
  30 void cpu_init_f(void)
  31 {
  32         gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  33         fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
  34         xlbarb_t *xlbarb = (xlbarb_t *) MMAP_XARB;
  35
  36         out_be32(&xlbarb->adrto, 0x2000);
  37         out_be32(&xlbarb->datto, 0x2500);
  38         out_be32(&xlbarb->busto, 0x3000);
  39
  40         out_be32(&xlbarb->cfg, XARB_CFG_AT | XARB_CFG_DT);
  41
  42         /* Master Priority Enable */
  43         out_be32(&xlbarb->prien, 0xff);
  44         out_be32(&xlbarb->pri, 0);
  45
  46 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
  47         out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
  48         out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
  49         out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
  50 #endif
  51
  52 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
  53         out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
  54         out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
  55         out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
  56 #endif
  57
  58 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
  59         out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
  60         out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
  61         out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
  62 #endif
  63
  64 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
  65         out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
  66         out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
  67         out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
  68 #endif
  69
  70 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
  71         out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
  72         out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
  73         out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
  74 #endif
  75
  76 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
  77         out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
  78         out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
  79         out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
  80 #endif
  81
  82 #ifdef CONFIG_FSL_I2C
  83         out_be16(&gpio->par_feci2cirq,
  84                 GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA);
  85 #endif
  86
  87         icache_enable();
  88 }
  89
  90 /*
  91  * initialize higher level parts of CPU like timers
  92  */
  93 int cpu_init_r(void)
  94 {
  95 #if defined(CONFIG_CMD_NET) && defined(CONFIG_FSLDMAFEC)
  96         MCD_initDma((dmaRegs *) (MMAP_MCDMA), (void *)(MMAP_SRAM + 512),
  97                     MCD_RELOC_TASKS);
  98 #endif
  99         return (0);
 100 }
 101
 102 void uart_port_conf(int port)
 103 {
 104         gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 105         u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40);
 106
 107         /* Setup Ports: */
 108         switch (port) {
 109         case 0:
 110                 out_8(&gpio->par_psc0, GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0);
 111                 break;
 112         case 1:
 113                 out_8(&gpio->par_psc1, GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1);
 114                 break;
 115         case 2:
 116                 out_8(&gpio->par_psc2, GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2);
 117                 break;
 118         case 3:
 119                 out_8(&gpio->par_psc3, GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3);
 120                 break;
 121         }
 122
 123         clrbits_8(pscsicr, 0x07);
 124 }
 125
 126 #if defined(CONFIG_CMD_NET)
 127 int fecpin_setclear(struct eth_device *dev, int setclear)
 128 {
 129         gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 130         struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
 131
 132         if (setclear) {
 133                 if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
 134                         setbits_be16(&gpio->par_feci2cirq, 0xf000);
 135                 else
 136                         setbits_be16(&gpio->par_feci2cirq, 0x0fc0);
 137         } else {
 138                 if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
 139                         clrbits_be16(&gpio->par_feci2cirq, 0xf000);
 140                 else
 141                         clrbits_be16(&gpio->par_feci2cirq, 0x0fc0);
 142         }
 143         return 0;
 144 }
 145 #endif