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git.ipfire.org Git - people/ms/u-boot.git/blob - arch/m68k/cpu/mcf547x_8x/cpu_init.c
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
9 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/immap.h>
17 #if defined(CONFIG_CMD_NET)
20 #include <asm/fsl_mcdmafec.h>
24 * Breath some life into the CPU...
26 * Set up the memory map,
27 * initialize a bunch of registers,
28 * initialize the UPM's
32 gpio_t
*gpio
= (gpio_t
*) MMAP_GPIO
;
33 fbcs_t
*fbcs
= (fbcs_t
*) MMAP_FBCS
;
34 xlbarb_t
*xlbarb
= (xlbarb_t
*) MMAP_XARB
;
36 out_be32(&xlbarb
->adrto
, 0x2000);
37 out_be32(&xlbarb
->datto
, 0x2500);
38 out_be32(&xlbarb
->busto
, 0x3000);
40 out_be32(&xlbarb
->cfg
, XARB_CFG_AT
| XARB_CFG_DT
);
42 /* Master Priority Enable */
43 out_be32(&xlbarb
->prien
, 0xff);
44 out_be32(&xlbarb
->pri
, 0);
46 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
47 out_be32(&fbcs
->csar0
, CONFIG_SYS_CS0_BASE
);
48 out_be32(&fbcs
->cscr0
, CONFIG_SYS_CS0_CTRL
);
49 out_be32(&fbcs
->csmr0
, CONFIG_SYS_CS0_MASK
);
52 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
53 out_be32(&fbcs
->csar1
, CONFIG_SYS_CS1_BASE
);
54 out_be32(&fbcs
->cscr1
, CONFIG_SYS_CS1_CTRL
);
55 out_be32(&fbcs
->csmr1
, CONFIG_SYS_CS1_MASK
);
58 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
59 out_be32(&fbcs
->csar2
, CONFIG_SYS_CS2_BASE
);
60 out_be32(&fbcs
->cscr2
, CONFIG_SYS_CS2_CTRL
);
61 out_be32(&fbcs
->csmr2
, CONFIG_SYS_CS2_MASK
);
64 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
65 out_be32(&fbcs
->csar3
, CONFIG_SYS_CS3_BASE
);
66 out_be32(&fbcs
->cscr3
, CONFIG_SYS_CS3_CTRL
);
67 out_be32(&fbcs
->csmr3
, CONFIG_SYS_CS3_MASK
);
70 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
71 out_be32(&fbcs
->csar4
, CONFIG_SYS_CS4_BASE
);
72 out_be32(&fbcs
->cscr4
, CONFIG_SYS_CS4_CTRL
);
73 out_be32(&fbcs
->csmr4
, CONFIG_SYS_CS4_MASK
);
76 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
77 out_be32(&fbcs
->csar5
, CONFIG_SYS_CS5_BASE
);
78 out_be32(&fbcs
->cscr5
, CONFIG_SYS_CS5_CTRL
);
79 out_be32(&fbcs
->csmr5
, CONFIG_SYS_CS5_MASK
);
82 #ifdef CONFIG_SYS_I2C_FSL
83 out_be16(&gpio
->par_feci2cirq
,
84 GPIO_PAR_FECI2CIRQ_SCL
| GPIO_PAR_FECI2CIRQ_SDA
);
91 * initialize higher level parts of CPU like timers
95 #if defined(CONFIG_CMD_NET) && defined(CONFIG_FSLDMAFEC)
96 MCD_initDma((dmaRegs
*) (MMAP_MCDMA
), (void *)(MMAP_SRAM
+ 512),
102 void uart_port_conf(int port
)
104 gpio_t
*gpio
= (gpio_t
*) MMAP_GPIO
;
105 u8
*pscsicr
= (u8
*) (CONFIG_SYS_UART_BASE
+ 0x40);
110 out_8(&gpio
->par_psc0
, GPIO_PAR_PSC0_TXD0
| GPIO_PAR_PSC0_RXD0
);
113 out_8(&gpio
->par_psc1
, GPIO_PAR_PSC1_TXD1
| GPIO_PAR_PSC1_RXD1
);
116 out_8(&gpio
->par_psc2
, GPIO_PAR_PSC2_TXD2
| GPIO_PAR_PSC2_RXD2
);
119 out_8(&gpio
->par_psc3
, GPIO_PAR_PSC3_TXD3
| GPIO_PAR_PSC3_RXD3
);
123 clrbits_8(pscsicr
, 0x07);
126 #if defined(CONFIG_CMD_NET)
127 int fecpin_setclear(struct eth_device
*dev
, int setclear
)
129 gpio_t
*gpio
= (gpio_t
*) MMAP_GPIO
;
130 struct fec_info_dma
*info
= (struct fec_info_dma
*)dev
->priv
;
133 if (info
->iobase
== CONFIG_SYS_FEC0_IOBASE
)
134 setbits_be16(&gpio
->par_feci2cirq
, 0xf000);
136 setbits_be16(&gpio
->par_feci2cirq
, 0x0fc0);
138 if (info
->iobase
== CONFIG_SYS_FEC0_IOBASE
)
139 clrbits_be16(&gpio
->par_feci2cirq
, 0xf000);
141 clrbits_be16(&gpio
->par_feci2cirq
, 0x0fc0);